# US 11,908,852 B2 · Layout designs of integrated circuits having backside routing tracks

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- Number: US 11,908,852 B2
- Document ID: US11908852B2
- Status: Granted
- Kind: B2
- Application number: 17/833,531
- Filed: 2022-06-06
- Published: 2022-10-06
- Granted: 2024-02-20
- Earliest claimed: 2020-07-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-An Lai; Shih-Wei Peng; Wei-Cheng Lin; Jiann-Tyng Tzeng
- Web page: https://patentgrep.com/patent/US11908852B2

## CPC

- H10D 89/10: Integrated device layouts
- H03K 19/17744: {for input/output signals}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/42: Vias, e.g. via plugs
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/975: {Wiring regions or routing}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a first transistor, a horizontal routing track extending in a first direction in a first metal layer, and a via connector conductively connecting the horizontal routing track to a first terminal of the first transistor. The integrated circuit also includes a backside routing track extending in the first direction in a backside metal layer, and a backside via connector conductively connecting the backside routing track to a second terminal of the first transistor. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. In the integrated circuit, either the first terminal or the second terminal is a gate terminal of the first transistor.

## Claims

### Claim 1

An integrated circuit comprising:
a semiconductor substrate;
a first transistor having a first terminal, a second terminal, and a third terminal;
a horizontal routing track extending in a first direction as a one-dimensional horizontal routing track in a first metal layer;
a via connector conductively connecting the horizontal routing track to the first terminal of the first transistor;
a backside routing track extending in the first direction as a one-dimensional backside routing track in a backside metal layer, wherein the backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate;
a backside via connector conductively connecting the backside routing track to the second terminal of the first transistor;
wherein either the first terminal or the second terminal is a gate terminal of the first transistor; and
a first gate-strip, extending in a second direction perpendicular to the first direction, overlapping a channel region of the first transistor and forming the gate terminal of the first transistor;
a first conductive segment, extending in the second direction, overlapping a source region of the first transistor and forming a source terminal of the first transistor; and
a second conductive segment, extending in the second direction, overlapping a drain region of the first transistor and forming a drain terminal of the first transistor.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first transistor on the semiconductor substrate has a channel region between the backside metal layer and the first metal layer.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the backside via connector passes through the semiconductor substrate.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the first terminal is the gate terminal of the first transistor, and the second terminal is a source terminal or a drain terminal of the first transistor.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the first terminal is a source terminal or a drain terminal of the first transistor, and the second terminal is the gate terminal of the first transistor.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the via connector connects the horizontal routing track to the first gate-strip, and wherein the backside via connector connects the backside routing track to either the first conductive segment or the second conductive segment.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the via connector connects the horizontal routing track to either the first conductive segment or the second conductive segment, and wherein the backside via connector connects the backside routing track to the first gate-strip.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the first transistor, the horizontal routing track, the backside routing track is within an AOI logic cell, a multiplexer cell, a flip-flop cell, or a logic-gates combo cell.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising a second horizontal routing track adjacent to the horizontal routing track, and wherein the backside routing track is positioned vertically between the horizontal routing track and the second horizontal routing track.

### Claim 10

An integrated circuit comprising:
a semiconductor substrate;
a first logic gate and a second logic gate formed with transistors having channel regions on the semiconductor substrate, a first output of the first logic gate being configured to generate a first output logic signal having a first output phase different from a first input phase of a first input logic signal at a first input of the first logic gate, and wherein the first output of the first logic gate is conductively connected to a second input of the second logic gate;
a horizontal routing track extending in a first direction in a first metal layer;
a first via connector conductively connecting the horizontal routing track to the first input of the first logic gate;
a backside routing track extending in the first direction in a backside metal layer, wherein the channel regions of the transistors are between the backside metal layer and the first metal layer; and
a backside via connector conductively connecting the backside routing track to the first output of the first logic gate.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.

### Claim 12 (depends on 10)

The integrated circuit of claim 10, wherein the first logic gate is one of a NAND gate, a NOR gate, or an inverter.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, wherein the second logic gate has an output conductively connected to a second horizontal routing track through a second via connector, a second output of the second logic gate being configured to generate a second output logic signal having a second output phase different from the first output logic signal at the first output of the first logic gate.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the second logic gate is one of a NAND gate, a NOR gate, or an inverter.

### Claim 15 (depends on 10)

The integrated circuit of claim 10, further comprising a second horizontal routing track adjacent to the horizontal routing track, and wherein the backside routing track is positioned vertically between the horizontal routing track and the second horizontal routing track.

### Claim 16

A method of fabricating an integrated circuit, the method comprising:
fabricating gate-strips extending in a second direction perpendicular to a first direction, wherein a gate-strip overlaps an active zone extending in the first direction at a first intersection and forms a gate terminal of a first transistor;
fabricating conductive segments extending in the second direction, wherein a conductive segment overlaps the active zone at a second intersection and forms a channel connecting terminal of the first transistor, the channel connecting terminal including either a source terminal or a drain terminal;
fabricating a horizontal routing track conductively connected to a first one of the gate terminals or the channel connecting terminal of the first transistor, wherein the horizontal routing track extends in the first direction in a first metal layer; and
fabricating a backside routing track conductively connected to a second one of the gate terminals or the channel connecting terminal of the first transistor, wherein the backside routing track extends in the first direction in a backside metal layer, and wherein the backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a front side via connector connecting the horizontal routing track to the gate terminal of the first transistor, and forming a backside via connector connecting the backside routing track to the channel connecting terminal of the first transistor.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming a front side via connector connecting the horizontal routing track to the channel connecting terminal of the first transistor, and forming a backside via connector connecting the backside routing track to the gate terminal of the first transistor.

### Claim 19 (depends on 16)

The method of claim 16, comprising:
fabricating the gate-strips in a layer between the backside metal layer and the first metal layer.

### Claim 20 (depends on 16)

The method of claim 16, comprising:
fabricating the gate-strips, the conductive segments, the horizontal routing track, the backside routing track, a front side via connector, and a backside via connector as a part of a circuit including an AOI logic, a multiplexer, a flip-flop, or a logic-gates combo.