# US 11,908,851 B2 · Semiconductor device having fin structure

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- Number: US 11,908,851 B2
- Document ID: US11908851B2
- Status: Granted
- Kind: B2
- Application number: 17/116,915
- Filed: 2020-12-09
- Published: 2021-03-25
- Granted: 2024-02-20
- Earliest claimed: 2017-11-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Shun-Li Chen; Chung-Te Lin; Hui-Zhong Zhuang; Pin-Dai Sue; Jung-Chan Yang
- Web page: https://patentgrep.com/patent/US11908851B2

## CPC

- H10D 89/10: Integrated device layouts
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/427: {Power or ground buses}
- H10W 20/432: {comprising crossing interconnections}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
forming a fin structure protruding from a substrate of the semiconductor device;
forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess;
forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and
forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a second conductive rail on the first conductive rail; and
electrically connecting the second conductive rail to a reference voltage.

### Claim 3 (depends on 2)

The method of claim 2, wherein a portion the first conductive line formed within the first recess is covered by the second conductive rail.

### Claim 4 (depends on 2)

The method of claim 2, wherein a portion the second conductive line formed within the second recess is covered by the second conductive rail.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first conductive material is polysilicon, and the second conductive material is metal.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first conductive rail extends in a direction parallel to the fin structure.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a third conductive line in the same layer as the first conductive rail, wherein the third conductive line extends across the fin structure to wrap a third portion of the fin structure different from the first portion and the second portion; and
removing a portion of the third conductive line to disconnect the third conductive line from the first conductive rail.

### Claim 8 (depends on 7)

The method of claim 7, wherein the third conductive line is formed between the first conductive line and the second conductive line.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
forming a conductive via on another portion of the third conductive line; and
forming a second conductive rail on the first conductive rail, wherein the second conductive rail is disposed in a same layer as the conductive via while separated from the conductive via.

### Claim 10

A method for forming a transistor structure, comprising:
forming a fin structure protruding from a substrate;
disposing a first conductive line, a second conductive line, a third conductive line and a fourth conductive line along a direction perpendicular to the fin structure to wrap a first predetermined region, a first source region, a gate region and a first drain region of the fin structure, respectively; and
disposing a first conductive rail in a same layer as the first conductive line and one of the second conductive line and the fourth conductive line, wherein the first conductive rail extends in a direction parallel to the fin structure to be laterally contacted by the first conductive line and the one of the second conductive line and the fourth conductive line.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
removing a portion of another of the second conductive line and the fourth conductive line to disconnect the first conductive rail from the another of the second conductive line and the fourth conductive line.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
removing a portion of the third conductive line to disconnect the first conductive rail from the third conductive line.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
forming a second conductive rail on the first conductive rail in the direction parallel to the fin structure; and
electrically connecting the second conductive rail to a reference voltage.

### Claim 14 (depends on 10)

The method of claim 10, further comprising:
forming a conductive via on the third conductive line; and
forming a second conductive rail on the first conductive rail, wherein the second conductive rail is disposed in a same layer as the conductive via while separated from the conductive via.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
forming a conductive via on the one of the second conductive line and the fourth conductive line; and
forming a second conductive rail on the first conductive rail, wherein the second conductive rail is disposed in a same layer as the conductive via while separated from the conductive via.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
disposing a fifth conductive line in the same layer as the first conductive rail to wrap a second predetermined region of the fin structure, wherein each of the second conductive line, the third conductive line and the fourth conductive line is disposed between the first conductive line and the fifth conductive line, and the first conductive rail is laterally contacted by the fifth conductive line.

### Claim 17

A method for forming a semiconductor device, comprising:
forming a fin structure protruding from a substrate of the semiconductor device;
forming a first conductive line on the substrate along a first direction to wrap a first portion of the fin structure;
forming a second conductive line on the substrate along the first direction to contact a second portion of the fin structure different from the first portion;
disposing a first conductive rail along a second direction different from the first direction to be laterally contacted by one end of the first conductive line and a portion of one end of the second conductive line; and
disposing a second conductive rail along the second direction to be laterally contacted by another portion of the one end of the second conductive line.

### Claim 18 (depends on 17)

The method of claim 17, wherein the one end of the first conductive line and the another portion of the one end of the second conductive line are covered by the second conductive rail.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming a third conductive line on the substrate along the first direction to contact a third portion of the fin structure different from the first portion and the second portion; and
removing a portion of the third conductive line to disconnect the third conductive line from the first conductive rail.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
forming a conductive via on the third conductive line, wherein the second conductive rail is disposed in a same layer as the conductive via while separated from the conductive via.