# US 11,908,843 B2 · Semiconductor package, method of bonding workpieces and method of manufacturing semiconductor package

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- Number: US 11,908,843 B2
- Document ID: US11908843B2
- Status: Granted
- Kind: B2
- Application number: 17/460,306
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-02-20
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Bingchien Wu; Wei-Jen Wu; Chun-Yen Lo
- Web page: https://patentgrep.com/patent/US11908843B2

## CPC

- H10W 90/00: Package configurations
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

## Claims

### Claim 1

A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns from a top view.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the first semiconductor device comprises a first top metal layer having a first circuit pattern and the first alignment pattern insulated from the first circuit pattern.

### Claim 3 (depends on 2)

The semiconductor package as claimed in claim 2, wherein the second semiconductor device comprises a second top metal layer facing the first top metal layer and having a second circuit pattern electrically connected to the first circuit pattern and the second alignment pattern insulated from the second circuit pattern.

### Claim 4 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a length of (n−1) scale pitches of the second scale pattern is equal to a length of (n) scale pitches of the first scale pattern.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.

### Claim 7 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the first alignment pattern further having a first alignment mark adjacent to the plurality of first scale patterns, and the second alignment pattern further having a second alignment mark adjacent to the plurality of second scale patterns.

### Claim 8 (depends on 7)

The semiconductor package as claimed in claim 7, wherein a contour of the first alignment mark is alignment with a contour of the second optical from a top view.

### Claim 9 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.

### Claim 10

A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns separated from one another and arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns separated from one another and arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

### Claim 11 (depends on 10)

The semiconductor package as claimed in claim 10, wherein a length of (n−1) scale pitches of the second scale pattern is equal to a length of (n) scale pitches of the first scale pattern.

### Claim 12 (depends on 10)

The semiconductor package as claimed in claim 10, wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.

### Claim 13 (depends on 10)

The semiconductor package as claimed in claim 10, wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.

### Claim 14 (depends on 10)

The semiconductor package as claimed in claim 10, wherein the first alignment pattern further having a first alignment mark adjacent to the plurality of first scale patterns, and the second alignment pattern further having a second alignment mark adjacent to the plurality of second scale patterns.

### Claim 15 (depends on 14)

The semiconductor package as claimed in claim 14, wherein a contour of the first alignment mark is alignment with a contour of the second optical from a top view.

### Claim 16 (depends on 10)

The semiconductor package as claimed in claim 10, wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.

### Claim 17

A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns arranged in a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, wherein a length of (n−1) scale pitches of the second scale patterns is equal to a length of (n) scale pitches of the first scale patterns.

### Claim 18 (depends on 17)

The semiconductor package as claimed in claim 17, wherein the plurality of first scale patterns are arranged in a zigzag manner deviated from the first direction, and the plurality of second scale patterns are arranged in a zigzag manner deviated from the second direction.

### Claim 19 (depends on 17)

The semiconductor package as claimed in claim 17, wherein a center of the plurality of first scale patterns is aligned with a center of the plurality of second scale patterns.

### Claim 20 (depends on 17)

The semiconductor package as claimed in claim 17, wherein the first semiconductor device comprises a plurality of first alignment marks arranged diagonally on the first semiconductor device, and the second semiconductor device comprises a plurality of second alignment marks arranged diagonally on the second semiconductor device.