# US 11,908,840 B2 · Low stress asymmetric dual side module

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- Number: US 11,908,840 B2
- Document ID: US11908840B2
- Status: Granted
- Kind: B2
- Application number: 17/823,164
- Filed: 2022-08-30
- Published: 2022-12-29
- Granted: 2024-02-20
- Earliest claimed: 2019-08-02
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Chee Hiong Chew; Atapol Prajuckamol; Stephen St. Germain; Yusheng Lin
- Web page: https://patentgrep.com/patent/US11908840B2

## CPC

- H10W 90/00: Package configurations
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/0198: {batch processes}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 40/778: {in encapsulations}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/076: {of strap connectors}
- H10W 72/07631: {Techniques}
- H10W 72/07636: {Soldering or alloying}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/631: {Shapes of strap connectors}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

## Claims

### Claim 1

A method of forming a semiconductor package, the method comprising:
providing a first panel of first substrates and a second panel of second substrates;
printing a first electrically conductive bonding material on a first side of the first panel of first substrates and a first side of the second panel of second substrates in predetermined locations;
coupling two or more die to each substrate of the first panel of first substrates and to each substrate of the second panel of second substrates at the predetermined locations;
dispensing a second electrically conductive material onto a second side of each of the two or more die;
coupling a clip to each of the two or more die;
electrically coupling the two or more die to each substrate of the first panel of first substrates and to each substrate of the second panel of second substrates;
singulating each of the first panel and the second panel into a plurality of first substrates and a plurality of second substrates, respectively;
dispensing solder onto a plurality of predetermined locations on the first side of each of the plurality of first substrates and each of the plurality of second substrates;
coupling a first substrate of the plurality of first substrates to a first side of a lead frame;
coupling two or more spacers to a first side of the first substrate; and
coupling a first side of a second substrate of the plurality of second substrates to the two or more spacers and to the second side of the lead frame;
wherein the first side of the first substrate and first side of the second substrate are asymmetrically coupled through the two or more spacers.

### Claim 2 (depends on 1)

The method of claim 1, further comprising trimming the lead frame to expose a plurality of leads and forming the leads.

### Claim 3 (depends on 1)

The method of claim 1, further comprising encapsulating the lead frame on the first side and the second side, wherein a second side of each substrate of the plurality of first substrates and the plurality of second substrates is exposed.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first panel of first substrates and the second panel of second substrates each comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

### Claim 5 (depends on 1)

The method of claim 1, further comprising coupling a heat sink with one of the second side of the first substrate of the plurality of first substrates, the second side of the second substrate of the plurality of second substrates, or any combination thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein the two or more spacers are comprised of electrically conductive material and electrically couple the first substrate to the second substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first and the second electrically conductive material comprises one of a solder paste or a sintering paste.

### Claim 8

A method of forming a semiconductor package, the method comprising:
coupling a first substrate to a lead frame;
coupling a spacer to the first substrate;
coupling a second substrate to the lead frame and the spacer, wherein the lead frame and the spacer are coupled between the first substrate and the second substrate upon coupling of the second substrate to the lead frame; and
partially encapsulating the lead frame in a molding compound;
wherein a perimeter of the first substrate only partially overlaps a perimeter of the second substrate and the perimeter of the second substrate only partially overlaps the perimeter of the first substrate when the first substrate and second substrate are coupled through the spacer.

### Claim 9 (depends on 8)

The method of claim 8, wherein only a portion of the first substrate is coupled directly under the second substrate and only a portion of the second substrate is coupled directly over the first substrate.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al2O3) ceramic doped with zirconium dioxide (ZrO2), a silicon nitride (Si3N4) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H—AlN) ceramic, or any combination thereof.

### Claim 11 (depends on 8)

The method of claim 8, further comprising coupling a heat sink with one of the first substrate, the second substrate, or any combination thereof.

### Claim 12 (depends on 8)

The method of claim 8, further comprising electrically coupling the first substrate to the second substrate through the spacer.

### Claim 13 (depends on 8)

The method of claim 8, wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

### Claim 14

A method of forming a semiconductor package, the method comprising:
asymmetrically coupling a first substrate to a second substrate through a lead frame and a spacer; and
at least partially encapsulating the lead frame in a molding compound.

### Claim 15 (depends on 14)

The method of claim 14, wherein an outer edge of the first substrate extends beyond a perimeter of the second substrate and an outer edge of the second substrate extends beyond a perimeter of the first substrate.

### Claim 16 (depends on 14)

The method of claim 14, further comprising coupling a heat sink with one of the first substrate, the second substrate, or any combination thereof.

### Claim 17 (depends on 14)

The method of claim 14, further comprising electrically coupling the first substrate to the second substrate through the spacer.

### Claim 18 (depends on 14)

The method of claim 14, wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.

### Claim 19 (depends on 14)

The method of claim 14, further comprising coupling a plurality of clips to the first substrate and the second substrate.

### Claim 20 (depends on 14)

The method of claim 14, wherein a perimeter of a first side of the first substrate extends outside of a perimeter of a first side of the second substrate and the perimeter of the first side of the second substrate extends outside of the perimeter of the first side of the first substrate, wherein the first side of the first substrate faces the first side of the second substrate.