# US 11,908,839 B2 · 3D semiconductor device, structure and methods with connectivity structures

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- Number: US 11,908,839 B2
- Document ID: US11908839B2
- Status: Granted
- Kind: B2
- Application number: 17/947,752
- Filed: 2022-09-19
- Published: 2023-02-09
- Granted: 2024-02-20
- Earliest claimed: 2017-09-24
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han; Brian Cronquist; Eli Lusky
- Web page: https://patentgrep.com/patent/US11908839B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/30: Die-attach connectors
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

## Claims

### Claim 1

A 3D device, the device comprising:
at least a first level comprising logic circuits;
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprises connectivity structures,
wherein said connectivity structures comprise at least one of the following:
a. differential signaling, or
b. radio frequency transmission lines, or
c. Surface Waves Interconnect (SWI) lines, and
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions; and
a plurality of vias disposed through said second level,
wherein said plurality of vias have a circumscribed diameter of less than 2 micrometers.

### Claim 2 (depends on 1)

The 3D device according to claim 1, A 3D device, the device comprising:
at least a first level comprising logic circuits; and
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprises connectivity structures,
wherein said connectivity structures comprise at least one of the following:
a. differential signaling, or
b. radio frequency transmission lines, or
c. Surface Waves Interconnect (SWI) lines
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions,
wherein said logic circuits comprise logic cells, and
wherein said connectivity structures provide connection between said logic cells which are greater than 40 mm apart.

### Claim 3

A 3D device, the device comprising:
at least a first level comprising logic circuits; and
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprise connectivity structures,
wherein said connectivity structures comprise at least one of the following:
a. differential signaling, or
b. radio frequency transmission lines, or
c. Surface Waves Interconnect (SWI) lines
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions,
wherein said device comprises a first device and a second device, each comprising said first level and said second level,
wherein said first level comprises a substrate comprising single crystal silicon,
wherein said first device has a substantially greater surface area than said second device, and
wherein a layout of a portion of said second level of said second device is identical to a portion of said second level of said first device.

### Claim 4 (depends on 1)

The 3D device according to claim 1, further comprising:
a plurality of vias disposed through said second level,
wherein said vias have a circumscribed diameter of less than 2 micrometers.

### Claim 5

A 3D device, the device comprising:
at least a first level comprising logic circuits; and
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprises connectivity structures,
wherein said device comprises Radio Frequency (“RF”) circuits to drive said connectivity structures,
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions,
wherein said logic circuits comprise logic cells, and
wherein said connectivity structures provide connection between said logic cells which are greater than 40 mm apart.

### Claim 6 (depends on 5)

The 3D device according to claim 5,
wherein said device comprises a first device and a second device, each comprising said first level and said second level,
wherein said first level comprises a substrate comprising single crystal silicon,
wherein said first device has a substantially greater surface area than said second device, and
wherein a layout of a portion of said second level of said second device is identical to a portion of said second level of said first device.

### Claim 7

A 3D device, the device comprising:
at least a first level comprising logic circuits; and
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprises connectivity structures,
wherein said first level comprises a substrate comprising single crystal silicon,
wherein said substrate comprises microchannels designed for fluid cooling,
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions, and
wherein said device comprises Radio Frequency (“RF”) circuits to drive said connectivity structures.

### Claim 8 (depends on 7)

The 3D device according to claim 7,
wherein said connectivity structures comprise at least one of the following:
a. differential signaling, or
b. radio frequency transmission lines, or
c. Surface Waves Interconnect (SWI) lines.

### Claim 9

A 3D device, the device comprising:
at least a first level comprising logic circuits; and
at least a second level bonded to said first level,
wherein said second level comprises a plurality of transistors,
wherein said device comprises connectivity structures,
wherein said first level comprises a substrate comprising single crystal silicon,
wherein said substrate comprises microchannels designed for fluid cooling,
wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions,
wherein said device comprises a first device and a second device, each comprising said first level and said second level,
wherein said first level comprises a substrate comprising single crystal silicon,
wherein said first device has a substantially greater surface area than said second device, and
wherein a layout of a portion of said second level of said second device is identical to a portion of said second level of said first device.