# US 11,908,838 B2 · Three-dimensional device structure including embedded integrated passive device and methods of making the same

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- Number: US 11,908,838 B2
- Document ID: US11908838B2
- Status: Granted
- Kind: B2
- Application number: 17/446,038
- Filed: 2021-08-26
- Published: 2023-03-02
- Granted: 2024-02-20
- Earliest claimed: 2021-08-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Jen-Yuan Chang; Chien-Chang Lee; Chia-Ping Lai; Tzu-Chung Tsai
- Web page: https://patentgrep.com/patent/US11908838B2

## CPC

- H10W 90/00: Package configurations
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 74/01: Manufacture or treatment
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

## Claims

### Claim 1

A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
a second die disposed on the first die and comprising a second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die;
a redistribution layer structure disposed on the second die and the DE layer; and
deep trench capacitor (DTC) disposed in a trench formed in the DE layer and electrically connected to the first die and the redistribution layer structure, the DTC comprising:
a first conductive layer electrically connected to the first die;
a second conductive layer electrically connected to the redistribution layer structure; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.

### Claim 2 (depends on 1)

The three-dimensional device structure of claim 1, wherein the DTC comprises a second dielectric layer surrounded by the second conductive layer.

### Claim 3 (depends on 1)

The three-dimensional device structure of claim 1, wherein:
the DTC comprises a contact flange comprising end regions of the first conductive layer, the first dielectric layer, and the second conductive layer that are disposed on an upper surface of the DE layer; and
the redistribution layer structure comprises a metal feature that electrically contacts the end region of the second conductive layer.

### Claim 4 (depends on 1)

The three-dimensional device structure of claim 1, wherein:
the redistribution layer structure comprises metal features; and
one of the metal features electrically contacts the second conductive layer.

### Claim 5 (depends on 1)

The three-dimensional device structure of claim 1, further comprising a through dielectric via (TDV) structure extending from an upper surface of the first die through the DE layer to electrically connect the first die and the redistribution layer structure.

### Claim 6 (depends on 5)

The three-dimensional device structure of claim 5, wherein the DTC is disposed between the TDV structure and the second die.

### Claim 7 (depends on 1)

The three-dimensional device structure of claim 1, further comprising multiple DTCs disposed in trenches formed in the DE layer.

### Claim 8 (depends on 1)

The three-dimensional device structure of claim 1, wherein:
the first die further comprises a first interconnect structure disposed on the first semiconductor substrate; and
the second die further comprises a second interconnect structure disposed on the second semiconductor substrate and electrically connected to the first interconnect structure.

### Claim 9

A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
second dies disposed on and electrically connected to the first die, each of the second dies comprising a respective second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second dies;
a redistribution layer structure disposed on the second dies and the DE layer;
through dielectric via (TDV) structures extending from an upper surface of the first die through the DE layer to electrically connect the first die and the redistribution layer structure; and
deep trench capacitors (DTC) disposed in respective trenches formed in the DE layer and electrically connected to the first die and the redistribution layer structure, wherein the DTCs are each disposed between one of the TDV structures and an adjacent one of the second dies, and each DTC comprises:
a first conductive layer electrically connected to the first die;
a second conductive layer electrically connected to the redistribution layer structure; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.

### Claim 10 (depends on 9)

The three-dimensional device structure of claim 9, wherein each DTC comprises a second dielectric layer surrounded by the second conductive layer.

### Claim 11 (depends on 9)

The three-dimensional device structure of claim 9, wherein:
each DTC comprises a contact flange comprising end regions of the first conductive layer, the first dielectric layer, and the second conductive layer that are disposed on an upper surface of the DE layer; and
the redistribution layer structure comprises metal features that electrically contact the end regions of the second conductive layers of the DTCs.

### Claim 12 (depends on 11)

The three-dimensional device structure of claim 11, wherein the redistribution layer structure comprises metal features embedded in a dielectric layer and electrically contacting the second conductive layers.

### Claim 13 (depends on 9)

The three-dimensional device structure of claim 9, wherein:
the first die further comprises a first interconnect structure disposed on the first semiconductor substrate; and
each of the second dies further comprises second interconnect structures disposed on the second semiconductor substrates and electrically connected to the first interconnect structure.

### Claim 14

A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate and a first interconnect structure electrically connected to a device layer of the first semiconductor substrate;
a second die disposed on the first die and comprising a second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die;
a redistribution layer structure disposed on the second die and the DE layer;
a deep trench capacitor (DTC) embedded in the DE layer and electrically connected to the first interconnect structure and the redistribution layer structure, the DTC comprising:
a first conductive layer electrically connected to the first die;
a second conductive layer electrically connected to the redistribution layer structure; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.

### Claim 15 (depends on 14)

The three-dimensional device structure of claim 14, further comprising:
a through dielectric via (TDV) structure embedded in the DE layer and electrically connected to the first interconnect structure and the redistribution layer structure.

### Claim 16 (depends on 15)

The three-dimensional device structure of claim 15, wherein the DTC is disposed between the TDV structure and the second die.

### Claim 17 (depends on 14)

The three-dimensional device structure of claim 14, wherein:
the redistribution layer structure comprises metal features embedded in a dielectric layer; and
one of the metal features electrically contacts the second conductive layer.

### Claim 18 (depends on 14)

The three-dimensional device structure of claim 14, wherein:
the DTC comprises a contact flange comprising end regions of the first conductive layer, the first dielectric layer, and the second conductive layer that are disposed on an upper surface of the DE layer; and
the redistribution layer structure comprises a metal feature that electrically contacts the end region of the second conductive layer.

### Claim 19 (depends on 14)

The three-dimensional device structure of claim 14, wherein the DTC comprises a second dielectric layer surrounded by the second conductive layer.

### Claim 20 (depends on 14)

The three-dimensional device structure of claim 14, further comprising multiple DTCs disposed in trenches formed in the DE layer.