# US 11,908,837 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,837 B2 - Document ID: US11908837B2 - Status: Granted - Kind: B2 - Application number: 17/409,519 - Filed: 2021-08-23 - Published: 2022-09-22 - Granted: 2024-02-20 - Earliest claimed: 2021-03-16 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Soichiro Ibaraki - Web page: https://patentgrep.com/patent/US11908837B2 ## CPC - H10W 90/00: Package configurations - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/25: against alpha rays, e.g. for outer space applications - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/695: Organic materials - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 42/271: {the arrangements being between stacked chips} - H10W 70/682: {comprising holes having chips therein} - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07352: {changes in structures or sizes} - H10W 72/075: {of bond wires} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/251: {Materials} - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 72/551: {Materials of bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In a semiconductor device, a first interposer has a first main surface. A second interposer is disposed on the first main surface. The second interposer has a second main surface on a side opposite to the first interposer. A material of the second interposer is different from that of the first interposer. A first semiconductor chip has a first front surface. The first semiconductor chip is mounted on the second main surface through a plurality of bump electrodes with the first front surface facing the second main surface. The first semiconductor chip includes a volatile memory circuit. A second semiconductor chip is mounted on a plurality of electrode patterns disposed on the first main surface or the second main surface through a plurality of bonding wires. The second interposer overlaps the first semiconductor chip in a direction perpendicular to the first main surface. ## Claims ### Claim 1 A semiconductor device comprising: a first interposer having a first main surface; a second interposer disposed on the first main surface, the second interposer having a second main surface on a side opposite to the first interposer, and formed of a material different from the first interposer; a first semiconductor chip having a first front surface facing the second main surface, the first semiconductor chip mounted on the second main surface using a plurality of bump electrodes, the first semiconductor chip further including a volatile memory circuit; and a second semiconductor chip mounted on a plurality of electrode patterns disposed on the first main surface or the second main surface through a plurality of bonding wires, wherein the second interposer overlaps the first semiconductor chip in a direction perpendicular to the first main surface, wherein the first interposer has an opening in the first main surface, and the second interposer is disposed within the opening. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first interposer contains radioactive material, and the second interposer has a higher radiation shielding ability than that of the first interposer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein a difference between a coefficient of linear expansion of the second interposer and a coefficient of linear expansion of the first semiconductor chip is smaller than a difference between a coefficient of linear expansion of the first interposer and the coefficient of linear expansion of the first semiconductor chip. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a thermal conductivity of the second interposer is higher than that of the first interposer. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the first interposer is an organic interposer and the second interposer is a semiconductor interposer. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein an area of the second interposer corresponds to an area of the first semiconductor chip. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the second interposer is thinner than the first interposer. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein a thickness of the second interposer is 58 μm or more. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein a thickness of the second interposer is 32 μm or more. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the opening has a planar shape. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the volatile memory circuit includes a memory controller. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor chip includes a memory chip. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip has a flip chip structure. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor chip is one of a plurality of second semiconductor chips stacked in a stepwise fashion. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the first semiconductor chip is disposed directly below a lowest stage of the plurality of second semiconductor chips. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor chip has a larger chip size than that of the first semiconductor chip. ### Claim 17 A semiconductor device comprising: a first interposer having a first main surface; a second interposer disposed on the first main surface, the second interposer having a second main surface on a side opposite to the first interposer, and formed of a material different from the first interposer; a first semiconductor chip having a first front surface facing the second main surface, the first semiconductor chip mounted on the second main surface using a plurality of bump electrodes, the first semiconductor chip further including a volatile memory circuit; and a second semiconductor chip mounted on a plurality of electrode patterns disposed on the first main surface or the second main surface through a plurality of bonding wires, wherein the second interposer overlaps the first semiconductor chip in a direction perpendicular to the first main surface, wherein the second main surface is flush with a top surface of the first interposer.