# US 11,908,836 B2 · Semiconductor package and method of manufacturing semiconductor package

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- Number: US 11,908,836 B2
- Document ID: US11908836B2
- Status: Granted
- Kind: B2
- Application number: 17/314,713
- Filed: 2021-05-07
- Published: 2022-07-14
- Granted: 2024-02-20
- Earliest claimed: 2021-01-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US11908836B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 46/301: {for alignment}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/874: {On different surfaces}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/016: {Cleaning}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

## Claims

### Claim 1

A method of forming a semiconductor package, comprising:
bonding a first die to a second die, wherein the first die comprises a plurality of first bonding pads, wherein the second die comprises a plurality of second bonding pads bonded to corresponding ones the plurality of first bonding pads, wherein the second die comprises a plurality of through vias electrically connected to corresponding ones of the plurality of second bonding pads;
forming an encapsulating material over the first die, wherein the encapsulating material laterally encapsulates the second die;
after bonding the first die to the second die, forming a plurality of alignment marks on the second die, wherein a pitch between adjacent two alignment marks of the plurality of alignment marks is different from a pitch between adjacent two through vias of the plurality of through vias; and
forming a redistribution structure over the second die and the encapsulating material.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
removing a back portion of a substrate of the second die, such that the plurality of through vias protrude from the substrate; and
providing an isolation layer over the substrate, wherein the isolation layer laterally encapsulates the plurality of through vias protruding from the substrate, and the plurality of alignment marks are formed in the isolation layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the plurality of alignment marks and forming the redistribution structure over the second die and the encapsulating material comprises:
forming recesses in a back surface of the second die; and
forming a dielectric layer over the second die and the encapsulating material, wherein the dielectric layer fills the recesses, wherein portions of the dielectric layer in the recesses form the plurality of alignment marks.

### Claim 4 (depends on 1)

The method of claim 1, wherein at least one of the alignment marks comprise a cross-shaped structure in a plan view.

### Claim 5 (depends on 1)

The method of claim 1, wherein the alignment marks comprise via shapes in a plan view.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the alignment marks comprises forming the alignment marks into a substrate of the second die.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the alignment marks comprises forming the alignment marks through a substrate of the second die.

### Claim 8

A method of forming a semiconductor package, the method comprising:
bonding a first die to a second die, wherein the first die comprises a plurality of first bonding pads, wherein the second die comprises a plurality of second bonding pads bonded to corresponding ones the plurality of first bonding pads;
after bonding the first die to the second die, forming an isolation layer on a side of the second die opposite the first die;
after forming the isolation layer, forming a plurality of alignment marks in the isolation layer on the second die; and
forming a redistribution structure over the isolation layer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising, prior to forming the isolation layer:
forming an encapsulant along sidewalls of the second die;
recessing the second die; and
forming the isolation layer on the second die.

### Claim 10 (depends on 8)

The method of claim 8, wherein the second die comprises a plurality of through vias, wherein a pitch between adjacent two alignment marks of the plurality of alignment marks is different from a pitch between adjacent two through vias of the plurality of through vias.

### Claim 11 (depends on 8)

The method of claim 8, wherein the plurality of alignment marks extend completely through the isolation layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the plurality of alignment marks extend completely through the isolation layer and into a substrate of the second die.

### Claim 13 (depends on 8)

The method of claim 8, wherein the plurality of alignment marks extend completely through the isolation layer and a substrate of the second die, wherein the plurality of alignment marks extend into an interconnection structure of the second die.

### Claim 14

A method of forming a semiconductor package, the method comprising:
bonding a first die to a second die, wherein the first die comprises a plurality of first bonding pads, wherein the second die comprises a plurality of second bonding pads bonded to corresponding ones the plurality of first bonding pads, wherein the second die comprises a plurality of through vias electrically connected to corresponding ones of the plurality of second bonding pads;
forming an encapsulating material over the first die, wherein the encapsulating material laterally encapsulates the second die;
recessing a surface of the second die to below an upper surface of the encapsulating material to form a recess;
forming an isolation layer in the recess on the second die;
forming a plurality of first alignment marks in the isolation layer, wherein a pitch between adjacent two first alignment marks of the plurality of first alignment marks is different from a pitch between adjacent two through vias of the plurality of through vias; and
forming a redistribution structure over the second die and the encapsulating material.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the redistribution structure comprises:
forming a first dielectric layer over the isolation layer; and
forming a second alignment mark in the first dielectric layer, wherein the second alignment mark overlaps at least one of the plurality of first alignment marks.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the redistribution structure further comprises:
forming a second dielectric layer over the first dielectric layer; and
forming a third alignment mark in the second dielectric layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein each of plurality of through vias comprise a liner and a fill material.

### Claim 18 (depends on 14)

The method of claim 14, wherein one or more of the plurality of first alignment marks form a pattern of a cross.

### Claim 19 (depends on 14)

The method of claim 14, wherein the second die comprises a through via, wherein a surface of the plurality of first alignment marks is level with a surface of the through via.

### Claim 20 (depends on 14)

The method of claim 14, wherein the plurality of first alignment marks extends through the isolation layer.