# US 11,908,834 B2 · Multi-chip package with reinforced isolation

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- Number: US 11,908,834 B2
- Document ID: US11908834B2
- Status: Granted
- Kind: B2
- Application number: 17/741,402
- Filed: 2022-05-10
- Published: 2022-08-25
- Granted: 2024-02-20
- Earliest claimed: 2020-03-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Vivek Arora; Woochan Kim
- Web page: https://patentgrep.com/patent/US11908834B2

## CPC

- H10W 70/40: Leadframes
- H10W 90/00: Package configurations
- H01F 27/06: Mounting, supporting, or suspending transformers, reactors, or choke coils {not being of the signal type}
- H01F 27/065: {Mounting on printed circuit boards}
- H01F 27/40: Structural association with built-in electric component, e.g. fuse
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/24: {characterised by materials}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/468: {Circuit boards}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/759: {between a chip and a laterally-adjacent discrete passive device}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES

## Abstract

A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

## Claims

### Claim 1

A multi-chip isolation (ISO) device package, comprising:
an interposer substrate comprising a top copper layer and a bottom metal layer, with a dielectric layer positioned between the top copper layer and the bottom metal layer;
a laminate transformer attached to the top copper layer positioned lateral to a first IC die and a second IC die;
bondwires wirebonding respective ones of first bond pads of the first IC die to first pads on the laminate transformer and to a first group of leads or lead terminals;
bondwires wirebonding respective ones of second bond pads of a second IC die to second pads on the laminate transformer and to a second group of leads or lead terminals; and
a mold compound providing encapsulation for the ISO device package, wherein the bottom metal layer is exposed from the ISO device package at least under the laminate transformer.

### Claim 2 (depends on 1)

The multi-chip package of claim 1, wherein the interposer substrate comprises a direct bonded copper (DBC) substrate so that the bottom metal layer comprises copper.

### Claim 3 (depends on 1)

The multi-chip package of claim 1, wherein the circuitry for the first IC die or for the second IC die further comprises a DC/DC converter.

### Claim 4 (depends on 1)

The multi-chip package of claim 1, wherein the laminate transformer supports a root mean square (RMS) breakdown voltage of at least 1 kV.

### Claim 5 (depends on 1)

The multi-chip package of claim 1, wherein the top copper layer comprises a patterned layer.

### Claim 6 (depends on 1)

The multi-chip package of claim 1, wherein the dielectric layer comprises a ceramic layer which provides a thermal conductivity at 20° C. of at least 20 W/m·K.

### Claim 7 (depends on 1)

The multi-chip package of claim 1, wherein the bottom metal layer is exposed from a bottom side or a topside of the ISO device package.

### Claim 8 (depends on 1)

The multi-chip package of claim 1, wherein the interposer substrate is not part of a leadframe.

### Claim 9 (depends on 1)

The multi-chip package of claim 1, wherein the dielectric layer is not patterned.

### Claim 10

A method for forming a multi-chip isolation (ISO) device package, comprising:
providing a laminate transformer;
wirebonding respective ones of first bond pads of a first IC die to first pads on the laminate transformer and to a first group of leads or lead terminals, and respective ones of second bond pads of a second IC die to second pads on the laminate transformer and to a second group of leads or lead terminals, and
covering the laminate transformer, the first IC die and the second IC die and at least a portion of the first group of leads or lead terminals and at least a portion of the second group of leads or lead terminals with mold material, wherein the bottom metal layer is exposed from the ISO device package at least under the laminate transformer.

### Claim 11 (depends on 10)

The method of claim 10, further including placing an interposer substrate comprising a top copper layer and a bottom metal layer with a dielectric layer positioned between the top copper layer and the bottom metal layer, between the first IC die, the second IC die, the laminate transformer and the first group of leads or lead terminals and the second group of leads or lead terminals.

### Claim 12 (depends on 10)

The method of claim 10, wherein the interposer substrate comprises a direct bonded copper (DBC) substrate so that the bottom metal layer comprises copper.

### Claim 13 (depends on 11)

The method of claim 11, wherein the top copper layer is a patterned layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein the laminate transformer supports a root mean square (RMS) breakdown voltage of at least 1 kV.

### Claim 15 (depends on 10)

The method of claim 10, wherein the dielectric layer comprises a ceramic layer which provides a thermal conductivity at 20° C. of at least 20 W/m·K.

### Claim 16 (depends on 10)

The method of claim 10, wherein the circuitry for the first IC die or for the second IC die further comprises a DC/DC converter.

### Claim 17

A method for forming a device package, comprising:
providing an interposer substrate comprising a top copper layer and a bottom metal layer with a dielectric layer positioned between the top copper layer and the bottom metal layer, and a leadframe including a plurality of leads or lead terminals;
placing the interposer substrate inside leads or lead terminals;
dispensing an adhesive onto at least the top copper layer;
placing a laminate transformer, a first IC die, and a second IC die, onto the adhesive;
wirebonding respective ones of the first bond pads of the first IC die to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and respective ones of the second bond pads of the second IC die to second pads on the laminate transformer and to a second group of the leads or the lead terminals, and
forming a mold material over the laminate transformer, the first IC die, and the second IC die, wherein the bottom metal layer is exposed from the ISO device package at least under the laminate transformer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the interposer substrate comprises a direct bonded copper (DBC) substrate so that the bottom metal layer comprises copper.

### Claim 19 (depends on 17)

The method of claim 17, wherein the laminate transformer supports a root mean square (RMS) breakdown voltage of at least 1 kV.

### Claim 20 (depends on 17)

The method of claim 17, wherein the circuitry for the first IC die or for the second IC die further comprises a DC/DC converter.