# US 11,908,833 B2 · Overlapping die stacks for nand package architecture

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- Number: US 11,908,833 B2
- Document ID: US11908833B2
- Status: Granted
- Kind: B2
- Application number: 17/723,386
- Filed: 2022-04-18
- Published: 2022-08-25
- Granted: 2024-02-20
- Earliest claimed: 2020-08-26
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Enyong Tai; Hem P. Takiar; Li Wang; Hong Wan Ng
- Web page: https://patentgrep.com/patent/US11908833B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/075: {of bond wires}
- H10W 72/50: Bond wires
- H10W 72/073: {of die-attach connectors}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/295: {optical coupling}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

## Claims

### Claim 1

A semiconductor assembly, comprising:
a substrate;
a first stack of semiconductor dies disposed directly over a first location on the substrate;
a first die attach film disposed between each semiconductor die in the first stack and having a first die attach film thickness;
a second stack of semiconductor dies disposed directly over a second location on the substrate,
wherein the first stack includes an uppermost semiconductor die of the first stack, and
wherein at least a portion of a semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack such that the semiconductor die of the second stack is not physically supported by the first stack; and
a second die attach film disposed between each semiconductor die in the second stack and having a second die attach film thickness different than the first die attach film thickness.

### Claim 2 (depends on 1)

The semiconductor assembly of claim 1 wherein the semiconductor die of the second stack is an uppermost semiconductor die of the second stack.

### Claim 3 (depends on 1)

The semiconductor assembly of claim 1, wherein the semiconductor die of the second stack has a smallest lateral distance to the first location among each semiconductor die of the second stack.

### Claim 4 (depends on 1)

The semiconductor assembly of claim 1, further comprising a dielectric spacer, controller die, or logic die disposed underneath a lowermost semiconductor die of the first stack or second stack.

### Claim 5 (depends on 1)

The semiconductor assembly of claim 1 wherein:
each semiconductor die of the first stack includes a first die thickness; and
each semiconductor die of the second stack includes a second die thickness different than the first die thickness.

### Claim 6 (depends on 1)

The semiconductor assembly of claim 1, further comprising:
a controller die disposed on the substrate between the first stack and second stack; and
a spacer within the second stack.

### Claim 7 (depends on 1)

The semiconductor assembly of claim 1 wherein:
the first stack includes a lowermost semiconductor die of the first stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the first stack; and
each upper semiconductor die of the first stack is offset from a semiconductor die directly below by a first offset in a first direction.

### Claim 8 (depends on 7)

The semiconductor assembly of claim 7, wherein:
the second stack includes a lowermost semiconductor die of the second stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the second stack; and
each upper semiconductor die of the second stack is offset from a semiconductor die directly below by a second offset in a second direction substantially opposite to the first direction.

### Claim 9 (depends on 1)

The semiconductor assembly of claim 1 wherein:
the first stack of semiconductor dies is electrically connected to a first subset of external connections by a first plurality of wirebonds; and
the second stack of semiconductor dies is electrically connected to a second subset of external connections by a second plurality of wirebonds.

### Claim 10

A semiconductor assembly, comprising:
a substrate;
a first stack of semiconductor dies disposed directly over a first location on the substrate;
a first die attach film disposed between each semiconductor die in the first stack and having a first die attach film thickness;
a second stack of semiconductor dies disposed directly over a second location on the substrate,
wherein the first stack includes an uppermost semiconductor die of the first stack,
wherein the second stack includes a nearest semiconductor die having a smallest lateral distance to the first location among each semiconductor die of the second stack, and
wherein at least a portion of the uppermost semiconductor die of the first stack is superimposed above at least a portion of the nearest semiconductor die of the second stack such that the uppermost semiconductor die of the first stack is not physically supported by the second stack; and
a second die attach film disposed between each semiconductor die in the second stack and having a second die attach film thickness different than the first die attach film thickness.

### Claim 11 (depends on 10)

The semiconductor assembly of claim 10, wherein the nearest semiconductor die of the second stack is an uppermost semiconductor die of the second stack.

### Claim 12 (depends on 10)

The semiconductor assembly of claim 10 wherein:
each semiconductor die of the first stack includes a first die thickness; and
each semiconductor die of the second stack includes a second die thickness different than the first die thickness.

### Claim 13 (depends on 10)

The semiconductor assembly of claim 10, further comprising a controller die disposed on the substrate between the first stack and second stack.

### Claim 14 (depends on 10)

The semiconductor assembly of claim 10 wherein:
the first stack includes a lowermost semiconductor die of the first stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the first stack; and
each upper semiconductor die of the first stack is offset from a semiconductor die directly below by a first offset in a first direction.

### Claim 15 (depends on 14)

The semiconductor assembly of claim 14 wherein:
the second stack includes a lowermost semiconductor die of the second stack and at least one upper semiconductor die stacked over the lowermost semiconductor die of the second stack; and
each upper semiconductor die of the second stack is offset from a semiconductor die directly below by a second offset in a second direction substantially opposite to the first direction.

### Claim 16 (depends on 10)

The semiconductor assembly of claim 10 wherein:
the first stack of semiconductor dies is electrically connected to a first subset of external connections by a first plurality of wirebonds; and
the second stack of semiconductor dies is electrically connected to a second subset of external connections by a second plurality of wirebonds.

### Claim 17

A method of manufacturing a semiconductor assembly, the method comprising:
providing a substrate;
stacking, over a first location on the substrate, a first plurality of semiconductor dies in a first stack, the first stack including an uppermost semiconductor die, wherein the first plurality of semiconductor dies are each attached by a first die attach film having a first thickness; and
stacking, over a second location on the substrate, a second plurality of semiconductor dies in a second stack,
wherein the second plurality of semiconductor dies are each attached by a second die attach film having a second thickness different than the first thickness,
wherein at least a portion of a semiconductor die of the second stack is superimposed above at least a portion of the uppermost semiconductor die of the first stack such that the semiconductor die of the second stack is not physically supported by the first stack.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
wirebonding the first and second pluralities of semiconductor dies to the substrate; and
providing an encapsulant to at least partially encapsulate the substrate, the first stack and the second stack.

### Claim 19 (depends on 18)

The method of claim 18, wherein the wirebonding includes:
wirebonding, subsequent to stacking the first and second stacks, the first and second pluralities of semiconductor dies to a first subset of external connections and a second subset of external connections, respectively.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
disposing a spacer at the second location on the substrate.