# US 11,908,831 B2 · Method for manufacturing a wafer level chip scale package (WLCSP)

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- Number: US 11,908,831 B2
- Document ID: US11908831B2
- Status: Granted
- Kind: B2
- Application number: 17/483,076
- Filed: 2021-09-23
- Published: 2022-04-21
- Granted: 2024-02-20
- Earliest claimed: 2020-10-21
- Assignees: Stmicroelectronics Pte Ltd
- Applicants: STMicroelectronics PTE LTD
- Inventors: Chun Yi Teng; David Gani
- Web page: https://patentgrep.com/patent/US11908831B2

## CPC

- H10W 20/01: {Manufacture or treatment}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/01257: {by reflowing}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/29: Bond pads specially adapted therefor
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

## Claims

### Claim 1

A process, comprising:
producing a front end of line (FEOL) substrate wafer which includes a semiconductor substrate wafer having a first thickness and a back surface and a premetallization dielectric layer;
producing back end of line (BEOL) structures over the premetallization dielectric layer, said BEOL structures including a first passivation layer including openings for bonding pads;
forming a redistribution layer over said first passivation layer, where the redistribution layer electrically connects the bonding pads to underbump metallization pads;
forming a second passivation layer including openings for the underbump metallization pads, and thus produce a production wafer;
opening trenches from a top surface of the production wafer that extend down to a depth that is only partially through the semiconductor substrate wafer;
prior to performing a bumping process at said underbump metallization pads, attaching a first handle to the top surface of the production wafer;
thinning at the back surface of the semiconductor substrate wafer of the production wafer from a first thickness to a second thickness that reaches the trenches and forms a plurality of wafer level chip scale packages;
attaching a second handle to bottom surfaces of said plurality of wafer level chip scale packages;
removing said first handle to expose the underbump metallization pads; and
performing said bumping process to form a solder ball at each of the exposed underbump metallization pads.

### Claim 2 (depends on 1)

The process of claim 1, wherein the second handle is made of a material that is heat resistant to a temperature of a heating reflow performed during the bumping process.

### Claim 3 (depends on 2)

The process of claim 2, wherein said temperature is at least 200° C.

### Claim 4 (depends on 1)

The process of claim 1, further comprising performing an ejectorless tape and reel process to remove individual ones of the wafer level chip scale packages from said second handle.

### Claim 5 (depends on 1)

The process of claim 1, wherein the second handle is made of a glass material.

### Claim 6 (depends on 1)

The process of claim 1, wherein the first handle is made of a glass material.

### Claim 7 (depends on 1)

The process of claim 1, wherein attaching the first handle to the top surface of the production wafer comprises performing a lamination.

### Claim 8 (depends on 1)

The process of claim 1, wherein attaching the second handle to bottom surfaces of said plurality of wafer level chip scale packages comprises performing a lamination.

### Claim 9 (depends on 1)

The process of claim 1, wherein attaching the first handle comprises bonding the first handle directly to a surface of the second passivation layer.

### Claim 10

A process, comprising:
opening trenches from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate, said trenches delimiting integrated circuit locations;
prior to performing a bumping process, attaching a first handle to the top surface of the production wafer;
thinning at a back surface of the semiconductor substrate to reach the trenches and form a wafer level chip scale package at each integrated circuit location;
attaching a second handle to a bottom surface of the thinned semiconductor substrate for the wafer level chip scale packages;
removing said first handle to expose underbump metallization pads at the top surface; and
performing said bumping process to form a solder ball at each of the exposed underbump metallization pads.

### Claim 11 (depends on 10)

The process of claim 10, further comprising, before the step of opening, producing said production wafer by:
performing a front end of line (FEOL) process;
performing a back end of line (BEOL) process;
forming a redistribution layer that electrically connects bonding pads produced in the BEOL process to the underbump metallization pads; and
forming a passivation layer including openings for the underbump metallization pads.

### Claim 12 (depends on 11)

The process of claim 11, wherein the second handle is made of a material that is heat resistant to a temperature of a heating reflow performed during the bumping process.

### Claim 13 (depends on 11)

The process of claim 11, wherein said temperature is at least 200° C.

### Claim 14 (depends on 11)

The process of claim 11, wherein attaching the first handle comprises bonding the first handle directly to a surface of the passivation layer.

### Claim 15 (depends on 10)

The process of claim 10, further comprising performing an ejectorless tape and reel process to remove individual ones of the wafer level chip scale packages from said second handle.

### Claim 16 (depends on 10)

The process of claim 10, wherein the second handle is made of a glass material.

### Claim 17 (depends on 10)

The process of claim 10, wherein the first handle is made of a glass material.

### Claim 18 (depends on 10)

The process of claim 10, wherein attaching the first handle to the top surface of the production wafer comprises performing a lamination.

### Claim 19 (depends on 10)

The process of claim 10, wherein attaching the second handle to bottom surfaces of said plurality of wafer level chip scale packages comprises performing a lamination.