# US 11,908,829 B2 · Integrated circuit package and method of forming same

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- Number: US 11,908,829 B2
- Document ID: US11908829B2
- Status: Granted
- Kind: B2
- Application number: 17/350,856
- Filed: 2021-06-17
- Published: 2022-09-29
- Granted: 2024-02-20
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yao-Te Huang; Hong-Wei Chan; Yung-Shih Cheng
- Web page: https://patentgrep.com/patent/US11908829B2

## CPC

- H10W 20/071: {of dielectric parts thereof}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/01338: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

## Claims

### Claim 1

A method comprising:
performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure;
performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition;
planarizing the first bonding layer;
forming a second bonding layer over a second substrate;
pressing the second bonding layer onto the first bonding layer; and
removing the first substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plasma power applied during the first plasma deposition is in a range of about 100 Watts to about 2000 Watts.

### Claim 3 (depends on 1)

The method of claim 1, wherein the buffer layer prevents plasma of the first plasma deposition from reaching the first interconnect structure during the first plasma deposition.

### Claim 4 (depends on 1)

The method of claim 1 further comprising, after removing the first substrate, forming a second interconnect structure over a second side of the first integrated circuit device.

### Claim 5 (depends on 4)

The method of claim 4, wherein a device layer interposes the first interconnect structure and the second interconnect structure.

### Claim 6 (depends on 5)

The method of claim 5 further comprises forming conductive connectors over the second interconnect structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein the buffer layer comprises undoped silicate glass.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first bonding layer comprises a high density plasma silicon oxide.

### Claim 9

A method comprising:
forming a device layer over a first substrate;
forming a first interconnect structure over the first substrate;
performing a low power plasma deposition to form a first dielectric layer over the first interconnect structure;
performing a high power plasma deposition to form a second dielectric layer over the first dielectric layer, the performing the high power plasma deposition comprising a plasma penetrating a portion of the first dielectric layer; and
attaching a second substrate to the second dielectric layer, the second substrate comprising a third dielectric layer disposed over a semiconductor substrate, and attaching the second substrate to the second dielectric layer comprises physically contacting the second dielectric layer to the third dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein a first conductive feature extends through an entirety of the second dielectric layer, wherein the second substrate further comprises a second conductive feature extending through an entirety of the third dielectric layer, and wherein attaching the second substrate comprises directly bonding the first conductive feature to the second conductive feature.

### Claim 11 (depends on 9)

The method of claim 9, wherein a first plasma power applied during the low power plasma deposition is in a range of between about 100 Watts and about 2000 Watts.

### Claim 12 (depends on 11)

The method of claim 11, wherein a second plasma power applied during the high power plasma deposition is in a range of between about woo Watts and about 10000 Watts.

### Claim 13 (depends on 9)

The method of claim 9, wherein conductive vias extend through at least a first portion of the first substrate, and further comprising:
after attaching the second substrate to the second dielectric layer, removing at least a second portion of the first substrate; and
after removing at least the portion of the first substrate, forming a second interconnect structure over the device layer, wherein the device layer is interposed between the first interconnect structure and the second interconnect structure.

### Claim 14 (depends on 9)

The method of claim 9, wherein the first dielectric layer is formed with a first thickness of greater than 600 nm.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second dielectric layer is formed with a second thickness of greater than 1400 nm, and further comprising planarizing the second dielectric layer to a third thickness of greater than 800 nm.

### Claim 16

A method comprising:
forming a first semiconductor device, the first semiconductor device comprising:
a semiconductor substrate;
an active device along a first side of the semiconductor substrate; and
an interconnect structure over the first side of the semiconductor substrate and electrically connected to the active device;
performing a first plasma process to deposit a buffer layer over the interconnect structure, the first plasma process utilizing a first power;
performing a second plasma process to deposit a first bonding layer over the buffer layer, the second plasma process utilizing a second power, the second power being greater than the first power;
attaching a substrate to the first bonding layer, the attaching the substrate comprising:
depositing a second bonding layer over the substrate; and
directly bonding the second bonding layer to the first bonding layer;
removing at least a portion of the semiconductor substrate; and
forming a first conductive feature along a second side of the semiconductor substrate.

### Claim 17 (depends on 16)

The method of claim 16, wherein the buffer layer has a greater thickness than the first bonding layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the first conductive feature is electrically connected to the active device.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
etching an opening through the first bonding layer and the buffer layer to expose the interconnect structure; and
forming a second conductive feature in the opening, the second conductive feature being electrically connected to the interconnect structure.

### Claim 20 (depends on 19)

The method of claim 19, further comprising a third conductive feature embedded in the second bonding layer, wherein the substrate comprises an integrated circuit die, and wherein attaching the substrate to the first bonding layer further comprises directly bonding the third conductive feature to the second conductive feature.