# US 11,908,821 B2 · Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging

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- Number: US 11,908,821 B2
- Document ID: US11908821B2
- Status: Granted
- Kind: B2
- Application number: 17/563,995
- Filed: 2021-12-28
- Published: 2022-04-21
- Granted: 2024-02-20
- Earliest claimed: 2017-12-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kristof Darmawikarta; Sri Ranga Sai Boyapati; Hiroki Tanaka; Robert A. May
- Web page: https://patentgrep.com/patent/US11908821B2

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

## Claims

### Claim 1

An integrated circuit (IC) package, comprising:
a level of metallization structures spaced apart within an area of the package;
a dielectric material over the level of metallization structures, wherein a first of the level of metallization structures comprises a bond pad on an embedded multichip interconnect bridge (EMIB) embedded within the dielectric material;
a plurality of first bond pad structures within the area of the package, wherein each of the first bond pad structures extends over a portion of the dielectric material, and comprises an integral via that is adjacent to a sidewall of the dielectric material and is in contact with a corresponding one of the level of metallization structures;
an IC die comprising a plurality of second bond pad structures within an area of the IC die; and
a plurality of interconnect structures that couple the first bond pad structures to the second bond pad structures.

### Claim 2 (depends on 1)

The IC package of claim 1, wherein individual ones of the first bond pad structures have a contiguous microstructure extending into the integral via.

### Claim 3 (depends on 1)

The IC package of claim 1, wherein individual ones of the first bond pad structures comprise a polycrystalline metal with one or more grains extending into the integral via.

### Claim 4 (depends on 1)

The IC package of claim 1, wherein the dielectric material is a first dielectric material, and the level of metallization structures comprises a second via embedded within a second dielectric material embedded below the dielectric material.

### Claim 5 (depends on 4)

The IC package of claim 4, wherein the second via is coupled to a metal trace in a second level of metallization structures adjacent to the EMIB.

### Claim 6 (depends on 1)

The IC package of claim 1, wherein the integral via comprises a seed layer material in contact with the corresponding one of the metallization structures.

### Claim 7 (depends on 6)

The IC package of claim 6, wherein the seed layer material lines the sidewall of the dielectric material and extends over the dielectric material.

### Claim 8 (depends on 7)

The IC package of claim 7, wherein the integral via further comprises a second material in contact with the seed layer material, and the seed layer material has a different composition than the second material, and wherein a top surface of the bond pad structures comprises the second material.

### Claim 9 (depends on 1)

The IC package of claim 1, wherein a center-to-center pitch of the first bond pad structures is less than 30 microns.

### Claim 10

A system comprising:
an integrated circuit (IC) package comprising:
an embedded multichip interconnect bridge (EMIB);
a plurality of levels of package metallization structures adjacent to the EMIB, and embedded within a first package dielectric material;
a second package dielectric material over the first package dielectric material and the levels of package metallization structures, and over the EMIB;
a plurality of first bond pad structures, wherein each of the first bond pad structures extends over a portion of the second package dielectric material, and comprises an integral via that is adjacent to a sidewall of the second package dielectric material, and wherein a first of the first bond pad structures is in contact with a top level of the package metallization structures, and wherein a second of the first bond pad structures is in contact with a metallization structure of the EMIB;
an IC die comprising a plurality of second bond pad structures; and
a plurality of interconnect structures that couple the first bond pad structures to the second bond pad structures.

### Claim 11 (depends on 10)

The system of claim 10, wherein the IC die comprises a processor and wherein the system further comprises a memory.

### Claim 12 (depends on 11)

The system of claim 11, wherein the memory also coupled to the EMIB.

### Claim 13 (depends on 11)

The system of claim 11, further comprises a wireless interface coupled to the processor to allow the processor to communicatively couple to a device external to the system.

### Claim 14 (depends on 11)

The system of claim 11, wherein individual ones of the first bond pad structures comprise a polycrystalline metal with one or more grains extending into the integral via.

### Claim 15 (depends on 11)

The system of claim 11, wherein the top level of the package metallization structures comprises a second via embedded within the first package dielectric material, and wherein the integral via is in direct contact with the second via.

### Claim 16 (depends on 15)

The system of claim 15, wherein the integral via comprises a seed layer material in contact with the second via.

### Claim 17 (depends on 16)

The system of claim 16, wherein the seed layer material lines the sidewall of the second package dielectric material and extends over the second package dielectric material.

### Claim 18 (depends on 10)

The system of claim 10, wherein individual ones of the first bond pad structures have a contiguous microstructure extending into the integral via.

### Claim 19 (depends on 10)

The system of claim 10, wherein the sidewall of the second package dielectric material adjacent to the integral via is substantially vertical.