# US 11,908,819 B2 · Semiconductor packaging substrate fine pitch metal bump and reinforcement structures

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- Number: US 11,908,819 B2
- Document ID: US11908819B2
- Status: Granted
- Kind: B2
- Application number: 18/046,134
- Filed: 2022-10-12
- Published: 2023-04-13
- Granted: 2024-02-20
- Earliest claimed: 2019-05-28
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Jun Chung Hsu; Chih-Ming Chung; Jun Zhai; Yifan Kao; Young Doo Jeon; Taegui Kim
- Web page: https://patentgrep.com/patent/US11908819B2

## CPC

- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01253: {by etching}
- H10W 72/01308: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/072: {of bump connectors}
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07311: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/07353: {changes in shapes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/383: {Reinforcing structures, e.g. collars}
- H10W 72/387: {Flow barriers}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

## Claims

### Claim 1

A semiconductor package comprising:
a packaging substrate including:
a plurality of metal routing layers;
a plurality of dielectric layers including a top dielectric layer forming a topmost surface;
a patterned metal contact layer, wherein the patterned metal contact layer includes:
an array of surface mount (SMT) metal bumps in a chip mount area, the array of SMT metal bumps partially embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and
a metal dam structure laterally surrounding the array of SMT metal bumps in the chip mount area, the metal dam structure partially embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and
a device bonded to the array of SMT metal bumps;
wherein the metal dam structure forms a first geometric shape adjacent a first edge and a second edge of the device, and a second geometric shape adjacent a corner of the device where the first edge intersects with the second edge.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the packaging substrate is a coreless packaging substrate.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the coreless packaging substrate further comprises a plurality of contact pads on a back side of the coreless packaging substrate.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the plurality of dielectric layers is a plurality of non-glass reinforced organic material layers.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the plurality of dielectric layers is a plurality of cured resin layers.

### Claim 6 (depends on 4)

The semiconductor package of claim 4, wherein the first geometric shape of the metal dam structure comprises a plurality of parallel metal lines running parallel to the first edge and the second edge of the device mounted on the array of SMT metal bumps.

### Claim 7 (depends on 4)

The semiconductor package of claim 4, further comprising an underfill material between the device and the packaging substrate.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the underfill material wicks along the first and second edges of the device such that an underfill height along the device first and second edges covers at least 50% of a thickness of the device.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the underfill material flashes outward from the device and is contained by the metal dam structure.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein the underfill material flashes outward and covers a first metal line of the plurality of parallel metal lines and does not cover all of the plurality of parallel metal lines.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the first metal line is located a lateral distance away from the edge of the device by a first keep out zone (KOZ1).

### Claim 12 (depends on 8)

The semiconductor package of claim 8, wherein:
each SMT metal bump includes straight sidewalls for a portion of the SMT metal bump that is embedded in the top dielectric layer and a portion of the SMT metal bump that extends above a topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump; and
the metal dam structure includes straight sidewalls for a portion of the metal dam structure that is embedded in the top dielectric layer and a portion of the metal dam structure that extends above a topmost surface of the top dielectric layer laterally adjacent to the metal dam structure.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the patterned metal contact layer includes a bulk metal layer and a surface finishing layer over the bulk metal layer.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, wherein the straight sidewalls for each SMT metal bump are continuously straight sidewalls spanning across both the portion of the SMT metal bump that is embedded in the top dielectric layer and the portion of the SMT metal bump that extends above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein for each SMT metal bump: a top surface of the bulk metal layer extends above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein for each SMT metal bump:
the straight sidewalls of the SMT metal bump are defined by the bulk metal layer; and
the surface finishing layer covers the top surface of the bulk metal layer and the straight sidewalls of the portion of the SMT metal bump that extends above the topmost surface of the top dielectric layer laterally adjacent to the SMT metal bump.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the surface finishing layer comprises a nickel layer, and the bulk metal layer comprises copper.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the surface finishing layer comprises a nickel-palladium-gold layer stack, and the bulk metal layer comprises copper.

### Claim 19 (depends on 16)

The semiconductor package of claim 16, wherein the device is bonded to the array of SMT metal bumps with an array of solder bumps.

### Claim 20 (depends on 16)

The semiconductor package of claim 16, wherein the device is a chip scale package.