# US 11,908,818 B2 · Semiconductor device

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- Number: US 11,908,818 B2
- Document ID: US11908818B2
- Status: Granted
- Kind: B2
- Application number: 17/525,593
- Filed: 2021-11-12
- Published: 2022-03-10
- Granted: 2024-02-20
- Earliest claimed: 2017-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sheng-Yu Wu; Ching-Hui Chen; Mirng-Ji Lii; Kai-Di Wu; Chien-Hung Kuo; Chao-Yi Wang; Hon-Lin Huang; Zi-Zhong Wang; Chun-Mao Chiu
- Web page: https://patentgrep.com/patent/US11908818B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductive bump over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall, the conductive bump has a bottom portion over the conductive pad and a top portion over the bottom portion;
a conductive cap over the conductive bump, wherein the bottom portion of the conductive bump is wider than the conductive cap and the top portion of the conductive bump; and
a passivation layer over the semiconductor substrate and laterally surrounding the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of the conductive cap.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the lower sidewall of the stepped sidewall structure is in contact with the passivation layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the upper sidewall of the stepped sidewall structure is spaced apart from the passivation layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the passivation layer has a portion extending along a top surface of the conductive pad and in contact with the lower sidewall of the stepped sidewall structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a sidewall of the conductive cap is aligned with the upper sidewall of the stepped sidewall structure of the conductive bump.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a sidewall of the conductive cap is misaligned with the lower sidewall of the stepped sidewall structure of the conductive bump.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the top surface of the conductive cap is flat.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein said portion of the passivation layer is below and spaced apart from the intermediary surface of the stepped sidewall structure.

### Claim 9 (depends on 4)

The semiconductor device of claim 4, wherein said portion of the passivation layer is in contact with the intermediary surface of the stepped sidewall structure.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductive bump over the conductive pad;
a conductive cap over the conductive bump, wherein a sidewall of the conductive cap is misaligned with a sidewall of the conductive bump; and
a passivation layer over the semiconductor substrate and surrounding the conductive bump, wherein the sidewall of the conductive bump has a lower portion in contact with the passivation layer and an upper portion spaced apart from the passivation layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a top surface of the conductive bump is lower than a top surface of the passivation layer.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein a bottom surface of the conductive cap is lower than a top surface of the passivation layer.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the sidewall of the conductive cap, a top surface of the conductive bump, and the sidewall of the conductive bump define a stepped sidewall structure.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the conductive bump has a bottom portion in contact with the conductive pad and a top portion in contact with the conductive cap, and a width of the bottom portion of the conductive bump is greater than a width of the conductive cap.

### Claim 15

A semiconductor device, comprising:
a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductive bump over the conductive pad, wherein the conductive bump has a bottom portion over the conductive pad and a top portion over the bottom portion, and the top portion is wider than the bottom portion;
a conductive cap over the top portion of the conductive bump, wherein the conductive cap has a curved top surface, and the top portion of the conductive bump has a curved top surface in contact with the conductive cap; and
a passivation layer over the semiconductor substrate and surrounding the conductive bump, wherein the passivation layer has a first portion in contact with the bottom portion of the conductive bump and a second portion over the first portion and spaced apart from the conductive cap, and a top surface of the second portion of the passivation layer is lower than the curved top surface of the conductive cap.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a bottom surface of the top portion of the conductive bump and a top surface of the first portion of the passivation layer face each other.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the conductive cap is wider than the bottom portion of the conductive bump.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the second portion of the passivation layer is spaced apart from the top portion of the conductive bump.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the first portion of the passivation layer is in contact with the top portion of the conductive bump.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the bottom surface of the top portion of the conductive bump is higher than the top surface of the first portion of the passivation layer and lower than the top surface of the second portion of the passivation layer.