# US 11,908,817 B2 · Bonding structure of dies with dangling bonds

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- Number: US 11,908,817 B2
- Document ID: US11908817B2
- Status: Granted
- Kind: B2
- Application number: 17/113,357
- Filed: 2020-12-07
- Published: 2021-04-22
- Granted: 2024-02-20
- Earliest claimed: 2018-11-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Ming-Fa Chen; Chih-Chia Hu
- Web page: https://patentgrep.com/patent/US11908817B2

## CPC

- H10W 72/90: Bond pads, in general
- H03K 19/1776: for memories
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H10W 46/301: {for alignment}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/01: {Manufacture or treatment}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

## Claims

### Claim 1

A package comprising:
a first die comprising:
a first semiconductor substrate;
a first through-via penetrating through the first semiconductor substrate; and
a first dielectric layer over and contacting the first semiconductor substrate;
a second dielectric layer over the first die;
a first active bond pad in the second dielectric layer, the first active bond pad is over and electrically coupling to the first through-via;
a first dummy bond pad in the second dielectric layer; and
a second die comprising:
a second active bond pad over and bonded to the first active bond pad; and
a dangling bond pad over and bonded to the first dummy bond pad.

### Claim 2 (depends on 1)

The package of claim 1, wherein the first die is a logic die, and the second die is a memory die.

### Claim 3 (depends on 1)

The package of claim 1, wherein the first active bond pad is a functional pad having currents flowing through, and the first dummy bond pad has voltages, and is configured not to have currents flowing through.

### Claim 4 (depends on 1)

The package of claim 1, wherein the first dummy bond pad is a terminal pad, with all bottom surfaces of the first dummy bond pad being in contact with dielectric materials.

### Claim 5 (depends on 4)

The package of claim 4, wherein all sidewalls of the first dummy bond pad are further in contact with additional dielectric materials.

### Claim 6 (depends on 1)

The package of claim 1 further comprising a die stack over and bonded onto the second die, wherein the die stack comprises a plurality of dies identical to the second die, and each of the plurality of dies comprises:
an additional active bond pad vertically aligned to the first active bond pad and the second active bond pad; and
an additional dangling bond pad over and vertically aligned to the first dummy bond pad.

### Claim 7 (depends on 1)

The package of claim 1 further comprising:
a second dummy bond pad in the second dielectric layer; and
a gap-filling dielectric material encircling the second die, wherein the gap-filling dielectric material contacts a top surface of the second dummy bond pad.

### Claim 8 (depends on 1)

The package of claim 1 further comprising:
a second dummy bond pad in the second dielectric layer; and
a dummy die over and bonding to the first die, wherein the dummy die comprises a third dummy bond pad over and bonded to the second dummy bond pad, and the second dummy bond pad and the third dummy bond pad are electrically floating.

### Claim 9

A package comprising:
a first die comprising:
a first semiconductor substrate;
a dielectric layer over the first semiconductor substrate;
a first dummy bond pad over the first die and in the dielectric layer; and
a second die comprising:
a second semiconductor substrate;
an integrated circuit at a surface of the second semiconductor substrate; and
a dangling bond pad over and bonded to the first dummy bond pad, wherein the dangling bond pad and the first dummy bond pad are electrically connected to the integrated circuit.

### Claim 10 (depends on 9)

The package of claim 9, wherein the first dummy bond pad is a terminal node of an electrical path comprising the integrated circuit, the dangling bond pad, and the first dummy bond pad.

### Claim 11 (depends on 9)

The package of claim 9, wherein the first die and the second die are configured so that voltages are provided to the first dummy bond pad, and no current flows through the first dummy bond pad.

### Claim 12 (depends on 9)

The package of claim 9 further comprising a dummy die over and bonded to the first die, wherein the first die further comprises a second dummy bond pad, and the dummy die further comprises a third dummy bond pad bonded the second dummy bond pad.

### Claim 13 (depends on 9)

The package of claim 9 further comprising a gap-filling dielectric material encircling and contacting the second die, wherein the first die further comprises a second dummy bond pad in physical contact with the gap-filling dielectric material.

### Claim 14 (depends on 9)

The package of claim 9 further comprising a plurality of dies over and stacked onto the second die, wherein each of the plurality of dies comprises:
an additional dangling bond pad bonding to an additional dummy pad in a respective underlying one of the plurality of dies.

### Claim 15 (depends on 14)

The package of claim 14, wherein the plurality of dies are identical to the second die.

### Claim 16

A package comprising:
a plurality of device dies forming a die stack, wherein each of the plurality of device dies comprises:
a semiconductor substrate;
a circuit at a surface of the semiconductor substrate;
a through-via penetrating through the semiconductor substrate;
a top surface dielectric layer;
a dummy bond pad in the top surface dielectric layer;
a bottom surface dielectric layer; and
a dangling bond pad in the bottom surface dielectric layer, wherein each of the dangling bond pad in an upper one of the plurality of device dies is bonded to the dummy bond pad in an underlying one of the plurality of device dies, and the dummy bond pad is a terminal node of an electrical path comprising the dummy bond pad, the dangling bond pad, and the circuit.

### Claim 17 (depends on 16)

The package of claim 16, wherein the plurality of device dies are memory dies.

### Claim 18 (depends on 16)

The package of claim 16 further comprising an additional die underlying and bonding to the die stack.

### Claim 19 (depends on 18)

The package of claim 18 further comprising a dummy die free from circuits therein, wherein the dummy die is over and bonded to the additional die, and the additional die comprises a first dummy bond pad, and the dummy die comprises a second dummy bond pad bonding to the first dummy bond pad.

### Claim 20 (depends on 16)

The package of claim 16, wherein the plurality of device dies are identical to each other.