# US 11,908,816 B2 · Method for fabricating semiconductor device with graphene layers

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- Number: US 11,908,816 B2
- Document ID: US11908816B2
- Status: Granted
- Kind: B2
- Application number: 17/538,133
- Filed: 2021-11-30
- Published: 2022-03-24
- Granted: 2024-02-20
- Earliest claimed: 2020-09-01
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tse-Yao Huang
- Web page: https://patentgrep.com/patent/US11908816B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 72/90: Bond pads, in general
- H10W 20/033: {in openings in dielectrics}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first passivation layer above the substrate;
forming a redistribution layer on the first passivation layer;
forming a first adjustment layer on the redistribution layer;
forming a pad layer on the first adjustment layer;
forming a second adjustment layer between the pad layer and the first adjustment layer; and
forming a second passivation layer on the first passivation layer;
wherein the first adjustment layer and the second adjustment layer are formed of graphene;
wherein forming the pad layer comprises: forming a lower portion on the first adjustment layer and forming an upper portion on the lower portion;
wherein the second adjustment layer is formed between the lower portion of the pad layer and the first adjustment layer, on sidewalls of the lower portion of the pad layer, and on bottom surfaces of the upper portion of the pad layer.

### Claim 2 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein the redistribution layer and the lower portion of the pad layer are formed in the second passivation layer, and the upper portion of the pad layer is formed on the second passivation layer.

### Claim 3 (depends on 2)

The method for fabricating a semiconductor device of claim 2, wherein forming the second passivation layer comprises: forming a lower layer on the first passivation layer and an upper layer on the lower layer, the redistribution layer is formed in the lower layer of the second passivation layer, and the lower portion of the pad layer is formed along the upper layer of the second passivation layer and extending to the lower layer of the second passivation layer.

### Claim 4 (depends on 3)

The method for fabricating a semiconductor device of claim 3, wherein the lower layer of the second passivation layer is formed of silicon oxide or phosphosilicate glass and the upper layer of the second passivation layer is formed of silicon nitride, silicon oxynitride, or silicon oxide nitride.

### Claim 5 (depends on 4)

The method for fabricating a semiconductor device of claim 4, further comprising: forming a first barrier layer between the redistribution layer and the first passivation layer.

### Claim 6 (depends on 5)

The method for fabricating a semiconductor device of claim 5, further comprising: forming a second barrier layer between the redistribution layer and the first adjustment layer.

### Claim 7 (depends on 6)

The method for fabricating a semiconductor device of claim 6, further comprising: forming a third barrier layer between the pad layer and the second adjustment layer.

### Claim 8 (depends on 7)

The method for fabricating a semiconductor device of claim 7, wherein the first barrier layer is formed of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

### Claim 9 (depends on 8)

The method for fabricating a semiconductor device of claim 8, further comprising: forming a topmost conductive line in the first passivation layer and a conductive via electrically connecting the redistribution layer and the topmost conductive line.

### Claim 10 (depends on 9)

The method for fabricating a semiconductor device of claim 9, wherein the first passivation layer comprises a bottom layer above the substrate and a top layer on the bottom layer, the topmost conductive line is in the bottom layer of the first passivation layer, and the conductive via is along the top layer of the first passivation layer and extending to the bottom layer of the first passivation layer.

### Claim 11 (depends on 10)

The method for fabricating a semiconductor device of claim 10, further comprising: forming first spacers on sidewalls of the first adjustment layer and sidewalls of the redistribution layer.

### Claim 12 (depends on 11)

The method for fabricating a semiconductor device of claim 11, further comprising: forming a bump unit on the pad layer.

### Claim 13 (depends on 12)

The method for fabricating a semiconductor device of claim 12, further comprising: forming an under bump metallization layer between the bump unit and the pad layer.

### Claim 14 (depends on 10)

The method for fabricating a semiconductor device of claim 10, further comprising: forming porous spacers on sidewalls of the first adjustment layer and sidewalls of the redistribution layer.

### Claim 15 (depends on 14)

The method of fabricating a semiconductor device of claim 14, wherein a porosity of the porous spacers is between about 50% and about 100%.

### Claim 16

A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a redistribution layer above the substrate;
forming a first adjustment layer on the redistribution layer;
forming a second adjustment layer on the first adjustment layer;
forming a pad layer on the second adjustment layer; and
forming first spacers on sidewalls of the first adjustment layer and on sidewalls of the redistribution layer;
wherein the first adjustment layer and the second adjustment layer are formed of graphene.

### Claim 17 (depends on 16)

The method for fabricating the semiconductor device of claim 16, further comprising a step of forming a first barrier layer above the substrate, wherein the redistribution layer is formed on the first barrier layer.