# US 11,908,812 B2 · Multi-die memory device with peak current reduction

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- Number: US 11,908,812 B2
- Document ID: US11908812B2
- Status: Granted
- Kind: B2
- Application number: 17/176,787
- Filed: 2021-02-16
- Published: 2022-06-23
- Granted: 2024-02-20
- Earliest claimed: 2020-12-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yui Shimizu; James E. Davis
- Web page: https://patentgrep.com/patent/US11908812B2

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 90/00: Package configurations
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 2207/105: Aspects related to pads, pins or terminals
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5434: {the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

## Claims

### Claim 1

A device comprising:
a substrate comprising a first substrate contact, a second substrate contact, and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;
a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the first substrate contact and the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and
a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first memory die and the second memory die comprise a same physical arrangement.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first ESD power clamp circuit comprises one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die.

### Claim 5 (depends on 1)

The device of claim 1, wherein the second ESD power clamp circuit does not contribute to a peak current level of the device during a power on operation of the device.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first substrate contact is electrically coupled to the first power supply contact pad and the first ESD power clamp contact pad by a single wirebond and a single solder ball.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first substrate contact is electrically coupled to the second power supply contact pad by a wirebond between the first power supply contact pad and the second power supply contact pad.

### Claim 8 (depends on 1)

The device of claim 1, wherein the second ESD power clamp circuit does not contribute to an overall current consumption level of the device.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die.

### Claim 10 (depends on 1)

The device of claim 1, wherein the first power supply contact pad corresponds to a ground voltage supply of the first memory die.

### Claim 11 (depends on 1)

The device of claim 1, wherein the first memory die comprises a third power supply contact pad.

### Claim 12 (depends on 11)

The device of claim 11, wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die and the third power supply contact pad corresponds to a ground voltage supply of the first memory die.

### Claim 13

A system comprising:
a controller; and
a memory device coupled to the controller, the memory device comprising:
a substrate comprising a first substrate contact a second substrate contact, and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;
a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and
a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

### Claim 14 (depends on 13)

The system of claim 13, wherein the first memory die and the second memory die comprise a same physical arrangement.

### Claim 15 (depends on 13)

The system of claim 13, wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

### Claim 16 (depends on 13)

The system of claim 13, wherein the first ESD power clamp circuit comprises one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die; and wherein the second ESD power clamp circuit does not contribute to a peak current level of the memory device during a power on operation of the memory device.

### Claim 17 (depends on 13)

The system of claim 13, wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die.

### Claim 18 (depends on 13)

The system of claim 13, wherein the first power supply contact pad corresponds to a ground voltage supply of the first memory die.

### Claim 19 (depends on 13)

The system of claim 13, wherein the first memory die comprises a third power supply contact pad; and wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die and the third power supply contact pad corresponds to a ground voltage supply of the first memory die.

### Claim 20

A semiconductor device comprising:
a substrate comprising a first substrate contact a second substrate contact and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;
a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and
a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.