# US 11,908,810 B2 · Hybrid semiconductor device and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,810 B2 - Document ID: US11908810B2 - Status: Granted - Kind: B2 - Application number: 17/489,328 - Filed: 2021-09-29 - Published: 2022-06-09 - Granted: 2024-02-20 - Earliest claimed: 2020-12-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Heungkyu Kwon; Junso Pak; Heeseok Lee - Web page: https://patentgrep.com/patent/US11908810B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/014: {using batch processing} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A hybrid semiconductor device includes an interposer substrate, a semiconductor package mounted on the interposer substrate, a molding member on the package substrate covering at least a portion of the semiconductor chip and exposing an upper surface of the semiconductor chip, and a stiffener disposed on an upper surface of the interposer substrate substantially around the semiconductor package. ## Claims ### Claim 1 A hybrid semiconductor device, comprising: an interposer substrate; a semiconductor package mounted on an upper surface of the interposer substrate, the semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, and a molding member on the package substrate covering a side surface of the semiconductor chip and exposing an upper surface of the semiconductor chip; and a stiffener disposed on the upper surface of the interposer substrate, wherein the stiffener is a walled structure that surrounds the semiconductor package, an inner surface of the walled structure faces towards and is spaced from an outer surface of the molding member, and an empty space exists from the inner surface of the walled structure and the outer surface of the molding member; and a heat sink having a flat lower surface in contact with the upper surface of the semiconductor package, the flat lower surface of the heat sink extending over and spaced above the wall structure of the stiffener. ### Claim 2 (depends on 1) The hybrid semiconductor device of claim 1, wherein an upper surface of the semiconductor chip is coplanar with an upper surface of the molding member. ### Claim 3 (depends on 1) The hybrid semiconductor device of claim 1, wherein the package substrate includes one of a coreless substrate and a core multilayered substrate. ### Claim 4 (depends on 1) The hybrid semiconductor device of claim 1, wherein the stiffener is a four-walled structure surrounding the semiconductor package and disposed in a peripheral region of the interposer substrate. ### Claim 5 (depends on 1) The hybrid semiconductor device of claim 1, wherein the interposer substrate includes a core multilayer substrate. ### Claim 6 (depends on 1) The hybrid semiconductor device of claim 1, wherein the semiconductor package further includes at least one of a first over passive device mounted on an upper surface of the package substrate and a first under passive device mounted on a lower surface of the package substrate. ### Claim 7 (depends on 6) The hybrid semiconductor device of claim 6, wherein the semiconductor package further includes package connection terminals disposed on the lower surface of the package substrate, and a height of the first under passive device is less than a height of the package connection terminals. ### Claim 8 (depends on 7) The hybrid semiconductor device of claim 7, further comprising: at least one of a second over passive device mounted on the upper surface of the interposer substrate and a second under passive device mounted on a lower surface of the interposer substrate; and interposer connection terminals disposed on the lower surface of the interposer substrate. ### Claim 9 (depends on 8) The hybrid semiconductor device of claim 8, wherein a pitch between the package connection terminals is less than a pitch between the interposer connection terminals. ### Claim 10 (depends on 1) The hybrid semiconductor device of claim 1, wherein the semiconductor package has a first height relative to an upper surface of the interposer substrate, and the stiffener has a second height relative to the upper surface of the interposer substrate and different from the first height. ### Claim 11 A hybrid semiconductor device, comprising: an interposer substrate; a semiconductor package disposed on an upper surface of the interposer substrate, the semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, and a molding member on the package substrate covering at least a portion of the semiconductor chip; a stiffener disposed on the upper surface of the interposer substrate, wherein the stiffener is a walled structure that surrounds the semiconductor package, an inner surface of the walled structure faces towards and is spaced from an outer surface of the molding member, and an empty space exists from the inner surface of the walled structure to the outer surface of the molding member; a heat sink having a flat lower surface in contact with the upper surface of the semiconductor package, the flat lower surface of the heat sink extending over and spaced above the wall structure of the stiffener; package connection terminals disposed between a lower surface of the semiconductor package and the upper surface of the interposer substrate; and interposer connection terminals disposed on a lower surface of the interposer substrate, wherein a pitch between the package connection terminals is less than a pitch between the interposer connection terminals. ### Claim 12 (depends on 11) The hybrid semiconductor device of claim 11, wherein an upper surface of the semiconductor chip is exposed by the molding member. ### Claim 13 (depends on 11) The hybrid semiconductor device of claim 11, wherein the package substrate is one of a coreless substrate and a core multilayered substrate. ### Claim 14 (depends on 11) The hybrid semiconductor device of claim 11, wherein the interposer substrate is a core multilayer substrate. ### Claim 15 (depends on 11) The hybrid semiconductor device of claim 11, wherein the semiconductor package has a first height relative to the upper surface of the interposer substrate, and the stiffener has a second height relative to the upper surface of the interposer substrate different from the first height. ### Claim 16 An electronic device, comprising: a main board; an interposer substrate disposed on the main board; a semiconductor package mounted on an upper surface of the interposer substrate, the semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, and a molding member on the package substrate covering at least a portion of the semiconductor chip; a stiffener disposed on the upper surface of the interposer substrate, wherein the stiffener is a walled structure that surrounds the semiconductor package, an inner surface of the walled structure faces towards and is spaced from an outer surface of the molding member, and an empty space exists from the inner surface of the walled structure to the outer surface of the molding member; package connection terminals interposed between a lower surface of the semiconductor package and the upper surface of the interposer substrate; interposer connection terminals interposed between a lower surface of the interposer substrate and an upper surface of the main board; and a heat sink having a flat lower surface in contact with the upper surface of the semiconductor package, the lower surface of the heat sink extending over and spaced above the wall structure of the stiffener. ### Claim 17 (depends on 16) The electronic device of claim 16, wherein a pitch between the package connection terminals is less than a pitch between the interposer connection terminals. ### Claim 18 (depends on 16) The electronic device of claim 16, wherein an upper surface of the semiconductor chip is exposed by the molding member. ### Claim 19 (depends on 16) The electronic device of claim 16, wherein the package substrate includes one of a coreless substrate and a core multilayered substrate. ### Claim 20 (depends on 16) The electronic device of claim 16, further comprising: second passive devices mounted on at least one of the upper surface and the lower surface of the interposer substrate.