# US 11,908,809 B2 · Crack sensor for sensing cracks in a solder pad, and method for production quality control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,809 B2 - Document ID: US11908809B2 - Status: Granted - Kind: B2 - Application number: 17/325,999 - Filed: 2021-05-20 - Published: 2021-09-02 - Granted: 2024-02-20 - Earliest claimed: 2017-12-06 - Assignees: STMicroelectronics (Crolles 2) SAS; STMicroelectronics (Grenoble 2) SAS - Applicants: STMicroelectronics (Crolles 2) SAS; STMicroelectronics (Grenoble 2) SAS - Inventors: Eric Sabouret; Krysten Rochereau; Olivier Hinsinger; Flore Persin-Crelerot - Web page: https://patentgrep.com/patent/US11908809B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9232: {with additional elements interposed between layers} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure. ## Claims ### Claim 1 A method, comprising: soldering a soldered element onto a solder pad of an integrated circuit; wherein said integrated circuit includes a structure underlying the solder pad, said structure including a network of first parallel metal tracks under and electrically connected to the solder pad and a detection electrical path formed by second metal tracks under the solder pad and insulated from and passing between the first parallel metal tracks; and testing production control of the integrated circuit by: performing a test on the detection electrical path to measure a quality which is indicative of a presence of a crack in the detection electrical path caused by soldering the soldered element onto the solder pad; and performing a decision phase based on the measured quality to generate a signal indicating whether said crack is present. ### Claim 2 (depends on 1) The method according to claim 1, wherein the measured quality is resistance of the detection electrical path between an input terminal and an output terminal. ### Claim 3 (depends on 2) The method according to claim 2, wherein performing the test comprises: applying one of an analog or digital signal to the input terminal of the detection electrical path; and receiving said analog or digital signal at the output terminal of the detection electrical path. ### Claim 4 (depends on 1) The method according to claim 1, wherein said structure underlying the solder pad comprises a plurality of metallization levels, and wherein said first parallel metal tracks and second metal tracks are formed in at least two levels of said plurality of metallization levels. ### Claim 5 (depends on 1) The method according to claim 1, wherein performing the decision phase comprises: comparing a value of the measured quality with a reference value; and generating the signal indicating presence of the crack if the measured quality value is different than the reference value. ### Claim 6 (depends on 5) The method according to claim 5, further comprising sorting the integrated circuit by either discarding or not discarding the integrated circuit in response to the generated signal. ### Claim 7 A method for testing an integrated circuit which comprises a structure underlying a solder pad, said structure including a network of first parallel metal tracks under and electrically connected to the solder pad and a detection electrical path formed by second metal tracks under the solder pad and insulated from and passing between the first parallel metal tracks, the method comprising: soldering a soldered element onto said solder pad; measuring a quality which is indicative of a presence of a crack in the detection electrical path produced by said soldering; and generating, in response to the measured quality, a signal indicating that said crack is present. ### Claim 8 (depends on 7) The method according to claim 7, wherein the measured quality is resistance of the detection electrical path between an input terminal and an output terminal. ### Claim 9 (depends on 8) The method according to claim 8, wherein measuring comprises: applying one of an analog or digital signal to the input terminal of the detection electrical path; and receiving said analog or digital signal at the output terminal of the detection electrical path. ### Claim 10 (depends on 7) The method according to claim 7, wherein generating comprises: comparing a value of the measured quality with a reference value; and generating the signal indicating that the crack is present when the measured quality value is different than the reference value. ### Claim 11 (depends on 7) The method according to claim 7, further comprising sorting the integrated circuit by either discarding or not discarding the integrated circuit in response to the generated signal.