# US 11,908,806 B2 · Semiconductor package and method of fabricating the same

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- Number: US 11,908,806 B2
- Document ID: US11908806B2
- Status: Granted
- Kind: B2
- Application number: 17/501,008
- Filed: 2021-10-14
- Published: 2022-05-26
- Granted: 2024-02-20
- Earliest claimed: 2020-11-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Ho Kim; Ji Hwang Kim; Hwan Pil Park; Jong Bo Shim
- Web page: https://patentgrep.com/patent/US11908806B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/013: {of die-attach connectors}
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/01515: {Forming coatings}
- H10W 72/075: {of bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

## Claims

### Claim 1

A semiconductor package, comprising:
a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern;
a first semiconductor chip placed on an upper surface of the first substrate;
a ball array structure that is placed on the upper surface of the first substrate, is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip and is spaced apart from side walls of the first semiconductor chip; and
a shielding structure that is in contact with an upper surface of the first semiconductor chip, is in contact with at least a part of an upper surface of the ball array structure and is not in contact with side surfaces of the ball array structure,
wherein the ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions, and
a maximum width in a first direction parallel to the upper surface of the first substrate of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion between adjacent solder ball portions.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a distance between adjacent solder ball portions is less than 0.05 times the maximum width of the solder ball portion in the first direction.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, further comprising:
an interposer placed on the shielding structure, wherein the interposer includes a second insulating layer and a second conductive pattern in the second insulating layer; and
a connection terminal disposed between the first substrate and the interposer, wherein the connection terminal electrically connects the first conductive pattern and the second conductive pattern,
wherein the maximum width of the solder ball portion in the first direction differs from a maximum width of the connection terminal.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the maximum width of the solder ball portion in the first direction is greater than the maximum width of the connection terminal.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first dam disposed on the upper surface of the first substrate, between the ball array structure and the first semiconductor chip along an inner perimeter of the ball array structure; and
a second dam disposed on the upper surface of the first substrate along an outer perimeter of the ball array structure.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first trench formed inside the upper surface of the first substrate wherein the first trench extends along a perimeter of the first semiconductor chip between the ball array structure and the side wall of the first semiconductor chip; and
a second trench formed inside the upper surface of the first substrate wherein the second trench extends along a perimeter of an outer wall of the ball array structure.

### Claim 7

A semiconductor package, comprising:
a first substrate that includes a first insulating layer, and a ground pattern and a first conductive pattern inside the first insulating layer;
a first semiconductor chip placed on an upper surface of the first substrate;
a ball array structure that is placed on the upper surface of the first substrate, is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip and is adjacent to the first semiconductor chip; and
a shielding structure that is placed on an upper surface of the first semiconductor chip and is in contact with at least a part of an upper surface of the ball array structure,
wherein the ball array structure has a closed loop shape and includes a material that differs from that of the shielding structure.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the upper surface of the ball array structure is substantially coplanar with the upper surface of the first semiconductor chip.

### Claim 9 (depends on 7)

The semiconductor package of claim 7, wherein the ball array structure includes a solder ball portion spaced apart from the first semiconductor chip, and a connecting portion that connects adjacent solder ball portions.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein a maximum width in a first direction parallel to the upper surface of the first substrate of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion between adjacent solder ball portions.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, further comprising:
a ground terminal placed on a lower surface of the first substrate wherein the ground terminal is electrically connected to the ground pattern and is placed on an outermost part of the first substrate.

### Claim 12 (depends on 9)

The semiconductor package of claim 9, wherein the shielding structure completely covers the upper surface of the ball array structure, and has a length that is substantially equal to a length of the first substrate, and
the semiconductor package further includes a molding film that is disposed between the shielding structure and the first substrate and wraps side surfaces of the first semiconductor chip and the ball array structure.

### Claim 13 (depends on 7)

The semiconductor package of claim 7, wherein the shielding structure includes either silver (Ag) or copper (Cu).

### Claim 14 (depends on 7)

The semiconductor package of claim 7, wherein the shielding structure includes a shielding layer, and an adhesive layer placed between the shielding layer and the first semiconductor chip.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the adhesive layer includes a heat transfer material.

### Claim 16 (depends on 7)

The semiconductor package of claim 7, further comprising
an interposer placed on the shielding structure, wherein the interposer includes a second insulating layer and a second conductive pattern in the second insulating layer; and
a connection terminal disposed between the first substrate and the interposer, wherein the connection terminal electrically connects the first conductive pattern and the second conductive pattern,
wherein a height of the ball array structure is less than a height of the connection terminal in a direction from the first substrate toward the interposer.

### Claim 17

A semiconductor package, comprising:
a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern;
a first semiconductor chip placed on an upper surface of the first substrate;
a ball array structure placed on the upper surface of the first substrate and adjacent to the first semiconductor chip, wherein the ball array structure is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip, and has a closed loop shape;
a shielding structure disposed on an upper surface of the first semiconductor chip, wherein the shielding structure is in contact with at least a part of an upper surface of the ball array structure and the upper surface of the first semiconductor chip;
an interposer placed on the shielding structure wherein the interposer includes a second insulating layer and a second conductive pattern placed in the second insulating layer;
a connection terminal placed between the first substrate and the interposer wherein the connection terminal electrically connects the first conductive pattern and the second conductive pattern;
a second substrate placed on the interposer; and
a second semiconductor chip placed on the second substrate wherein the second semiconductor chip is electrically connected to the first substrate through the second substrate, the interposer, and the connection terminal,
wherein the ball array structure includes a solder ball portion that is spaced apart from the first semiconductor chip, and a connecting portion that connects adjacent solder ball portions,
a maximum width in a first direction parallel to the upper surface of the first substrate of the solder ball portion is greater than a maximum width of the connecting, portion in a direction perpendicular to an extension direction of the connecting portion between adjacent solder ball portions, and is greater than a maximum width of the connection terminal, in the first direction, and
the shielding structure includes a material that differs from that of the ball array structure.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the maximum width of the solder ball portion is less than 500 μm, and
a distance between adjacent solder ball portions is less than 25 μm.

### Claim 19 (depends on 1)

The semiconductor package of claim 1, wherein the maximum with of the solder ball portion in the first direction is less than 500 μm.