# US 11,908,805 B2 · Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,805 B2 - Document ID: US11908805B2 - Status: Granted - Kind: B2 - Application number: 17/071,951 - Filed: 2020-10-15 - Published: 2021-01-28 - Granted: 2024-02-20 - Earliest claimed: 2018-12-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Avishesh Dhakal; Gary A. Monroe - Web page: https://patentgrep.com/patent/US11908805B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 42/267: {Patterned shielding planes} - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/014: {using batch processing} - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 72/0198: {batch processes} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference. ## Claims ### Claim 1 A semiconductor device, comprising: a package substrate having a ground plane, a first surface having a die attach area, and a second surface opposite the first surface; and a conformal coating positioned over a side of the first surface opposite the second surface, and extending along a side of the package substrate from the first surface to the second surface where the conformal coating is electrically coupled to the ground plane through an opening in the second surface of the package substrate. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the ground plane is recessed within the opening in the second surface of the package substrate. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the conformal coating is electrically coupled directly to the ground plane. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the package substrate further includes a conductive trace that extends from the ground plane to the second surface of the package substrate, and wherein the conformal coating is electrically coupled to the ground plane via the conductive trace. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the conformal coating is electrically coupled to the conductive trace at the second surface of the package substrate. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the opening is a trench or moat, and wherein the semiconductor device includes solder mask between the package substrate and the conformal coating. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the opening extends around a perimeter of the package substrate. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device further comprises a molded material covering at least a portion of the package substrate; the molded material includes a top surface; the molded material and the package substrate include a plurality of side surfaces; and the conformal coating coats the top surface and the plurality of side surfaces. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising a semiconductor die coupled to the first surface of the package substrate. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the conformal coating is configured to shield the semiconductor die from electromagnetic interference. ### Claim 11 A package substrate, comprising: a plurality of substrates and/or dielectric materials, wherein the plurality of substrates and/or dielectric materials includes: a first substrate and/or dielectric material having a first surface, the first surface (i) being a topmost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials, (ii) located at a first side of the package substrate, and (iii) including a die attach area, and a second substrate and/or dielectric material having a second surface, the second surface (i) being a bottommost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials and (ii) located at a second side of the package substrate opposite the first side; and a ground plane positioned between the first surface and the second surface, wherein the ground plane is exposed via an opening in the bottommost surface. ### Claim 12 (depends on 11) The package substrate of claim 11, wherein: the ground plane is recessed within the opening in the second surface of the package substrate; and/or the package substrate further includes a conductive trace that extends from the ground plane to the second surface of the package substrate. ### Claim 13 (depends on 12) The package substrate of claim 12, wherein: the opening is a trench or moat; and/or the opening extends around a perimeter of the package substrate.