# US 11,908,804 B2 · Array substrate and display panel

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- Number: US 11,908,804 B2
- Document ID: US11908804B2
- Status: Granted
- Kind: B2
- Application number: 16/759,343
- Filed: 2019-12-17
- Published: 2021-06-10
- Granted: 2024-02-20
- Earliest claimed: 2019-12-10
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Linfeng Liu; Aihua Tang; Yanxi Ye; Chihming Yang; Yunglun Lin
- Web page: https://patentgrep.com/patent/US11908804B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides an array substrate and a display panel. The array substrate includes a substrate, a first metal layer, a second metal layer, a pixel electrode layer, and an alignment identification terminal that are sequentially stacked. The alignment identification terminal is disposed in at least one of the first metal layer and the second metal layer, and is at least partially disposed in a sub-pixel electrode region. An arrangement of the alignment identification terminal is no longer limited by a narrow frame, and a size can be made larger to meet the needs of a CCD identification, ensuring an accuracy of identification and alignment.

## Claims

### Claim 1

An array substrate, comprising:
a base;
a first metal layer formed on the base wherein the first metal layer is patterned to form a first metal line and a first alignment identification terminal, the first metal line comprises a first gate signal line and a second gate signal line;
a second metal layer formed on the first metal layer; wherein the second metal layer is patterned to form a second metal line and a second alignment identification terminal, the second metal line comprises a first data signal line, a second data signal line, a signal connection line, and a third data signal line; and
a pixel electrode layer formed on the second metal layer, wherein the pixel electrode layer is patterned to form a pixel electrode, and the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode each has four domains;
wherein the first alignment identification terminal is integrally formed with the second gate signal line, wherein the first alignment identification terminal is used for alignment identification in the array substrate, and to transfer gate signals;
wherein the second alignment identification terminal is integrally formed with the third data signal line, wherein the second alignment identification terminal is used for alignment identification in the array substrate, and to transfer data signals;
wherein the first alignment identification terminal and the second alignment identification terminal are disposed opposite with each other, and projections of the first alignment identification terminal and the second alignment identification terminal on the base coincide; wherein first portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the first sub-pixel electrode, second portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the second sub-pixel electrode, and central portions of the first alignment identification terminal and the second alignment identification terminal are disposed in non-pixel electrode region between the first sub-pixel electrode and the second sub-pixel electrode.

### Claim 2 (depends on 1)

The array substrate as claimed in claim 1, wherein the first metal layer is a gate metal layer, and the second metal layer is a source-drain metal layer.

### Claim 3 (depends on 1)

The array substrate as claimed in claim 1, wherein a shape of the first alignment identification terminal is a cross shape; and a shape of the second alignment identification terminal is a cross shape.

### Claim 4

A display panel, comprising:
an array substrate, wherein the array substrate comprises:
a base;
a first metal layer formed on the base; wherein the first metal layer is patterned to form a first metal line and a first alignment identification terminal, the first metal line comprises a first gate signal line and a second gate signal line;
a second metal layer formed on the first metal layer; wherein the second metal layer is patterned to form a second metal line and a second alignment identification terminal, the second metal line comprises a first data signal line, a second data signal line, a signal connection line, and a third data signal line; and
a pixel electrode layer formed on the second metal layer, wherein the pixel electrode layer is patterned to form a pixel electrode, and the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode each has four domains;
wherein the first alignment identification terminal is integrally formed with the second gate signal line, wherein the first alignment identification terminal is used for alignment identification in the array substrate, and to transfer gate signals;
wherein the second alignment identification terminal is integrally formed with the third data signal line, wherein the second alignment identification terminal is used for alignment identification in the array substrate, and to transfer data signals;
wherein the first alignment identification terminal and the second alignment identification terminal are disposed opposite with each other, and projections of the first alignment identification terminal and the second alignment identification terminal on the base coincide; wherein first portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the first sub-pixel electrode, second portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the second sub-pixel electrode, and central portions of the first alignment identification terminal and the second alignment identification terminal are disposed in a non-pixel electrode region between the first sub-pixel electrode and the second sub-pixel electrode.

### Claim 5 (depends on 4)

The display panel as claimed in claim 4, wherein the first metal layer is a gate metal layer, and the second metal layer is a source-drain metal layer.

### Claim 6 (depends on 4)

The display panel as claimed in claim 4, wherein a shape of the first alignment identification terminal is a cross shape; and a shape of the second alignment identification terminal is a cross shape.