# US 11,908,802 B2 · Multi-chip package with high density interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,802 B2 - Document ID: US11908802B2 - Status: Granted - Kind: B2 - Application number: 17/842,600 - Filed: 2022-06-16 - Published: 2022-10-06 - Granted: 2024-02-20 - Earliest claimed: 2020-06-17 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Aleksandar Aleksov; Adel A. Elsherbini; Kristof Darmawikarta; Robert A. May; Sri Ranga Sai Boyapati - Web page: https://patentgrep.com/patent/US11908802B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/00: Package configurations - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/63: Vias, e.g. via plugs - H10W 70/635: {Through-vias} - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07254: {changes in dispositions} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed. ## Claims ### Claim 1 An apparatus comprising: a plurality of dielectric layers forming a substrate; a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate; a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate; a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site; and a plurality of second conductive interconnects disposed within the substrate to couple a third grouping of the plurality of second conductive contacts associated with the first die site with a first grouping of the plurality of second conductive contacts associated with a third die site, wherein the first and third groupings of the plurality of second conductive contacts associated with the first die site are on a same side of the first die site and are separated by a plurality of first conductive contacts. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the conductive interconnects to couple the first groupings comprise signal traces and the conductive interconnects to couple the second groupings comprise one or more conductive sheets. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein each die site is coupled with one or more dies. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the plurality of conductive contacts having a third pitch spacing on the bottom surface of the substrate comprise ball grid array (BGA) contacts. ### Claim 5 A system comprising: a display subsystem; a wireless communication interface; and a multi-chip package, the multi-chip package comprising: one or more processor dies; one or more memory dies; and a substrate coupled with the processor and memory dies, wherein the substrate comprises: top surface contacts arranged as coupling sites for the processor and memory dies, wherein at least one coupling site contains at least a first contact pitch and a second contact pitch higher than the first contact pitch; bottom surface contacts at a third contact pitch, wherein the third contact pitch is lower than the first contact pitch; and interconnects embedded within dielectric material, wherein the interconnects couple some of the top surface contacts with the bottom surface contacts and couple groupings of the top surface contacts having the second contact pitch along sides of a plurality of coupling sites with groupings of the top surface contacts along sides of adjacent coupling sites, wherein the interconnects further couple inner groupings of top surface contacts of adjacent coupling sites by extending deeper within the dielectric material. ### Claim 6 (depends on 5) The system of claim 5, further comprising two adjacent processor dies coupled together along flanking sides by high density interconnects within the substrate. ### Claim 7 (depends on 6) The system of claim 6, further comprising two memory dies coupled by high density interconnects within the substrate with one processor die along a same side. ### Claim 8 (depends on 7) The system of claim 7, further comprising a third memory die coupled by high density interconnects within the substrate with the processor die along a different side. ### Claim 9 (depends on 5) The system of claim 5, wherein one of more of the memory dies comprises a vertical stack of HBM. ### Claim 10 (depends on 5) The system of claim 5, wherein the interconnects further comprise a ground plane within the substrate in a layer below signal traces. ### Claim 11 A method comprising: forming multiple substrates on both sides of a peelable carrier, each substrate comprising: a plurality of dielectric layers; a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate; a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate; a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; and a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site; attaching integrated circuit dies to the die sites on the substrate; and peeling multi-chip packages from the carrier. ### Claim 12 (depends on 11) The method of claim 11, wherein attaching integrated circuit dies further comprises attaching a stack of HBM dies. ### Claim 13 (depends on 11) The method of claim 11, wherein the conductive interconnects to couple the first groupings comprise signal traces and the conductive interconnects to couple the second groupings comprise one or more conductive sheets. ### Claim 14 (depends on 11) The method of claim 11, further comprising covering the dies with a mold compound. ### Claim 15 (depends on 11) The method of claim 11, further comprising removing the mold compound from above a top surface of at least one die. ### Claim 16 (depends on 11) The method of claim 11, further comprising forming bumps over the conductive contacts on the bottom surface of the substrate. ### Claim 17 An apparatus comprising: a plurality of dielectric layers forming a substrate; a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate; a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate; a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; and a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings comprise signal traces and the conductive interconnects to couple the second groupings comprise one or more conductive sheets. ### Claim 18 An apparatus comprising: a plurality of dielectric layers forming a substrate; a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate; a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate; a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site; and third and fourth groupings of the plurality of second conductive contacts associated with the first and second die sites coupled by a plurality of second conductive interconnects disposed within adjacent layers in the substrate. ### Claim 19 A method comprising: forming a substrate on a peelable carrier, the substrate comprising: a plurality of dielectric layers; a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate; a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate; a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; and a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site; attaching integrated circuit dies to the die sites on the substrate; forming bumps over the conductive contacts on the bottom surface of the substrate; and peeling multi-chip packages from the carrier.