# US 11,908,800 B2 · Semiconductor structure

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- Number: US 11,908,800 B2
- Document ID: US11908800B2
- Status: Granted
- Kind: B2
- Application number: 17/871,738
- Filed: 2022-07-22
- Published: 2022-11-17
- Granted: 2024-02-20
- Earliest claimed: 2021-01-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ya-Chin Chiu; Ming-Hsien Lin; Chia-Tung Hsu; Lun-Chieh Chiu
- Web page: https://patentgrep.com/patent/US11908800B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/07255: {changes in materials}
- H10W 72/2528: {Intermetallic compounds}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.

## Claims

### Claim 1

A semiconductor structure comprising:
a multi-level interconnect structure;
a passivation layer above the multi-level interconnect structure;
a barrier layer lining an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure, wherein the barrier layer comprises:
a first layer in a nano-crystalline phase;
a second layer above the first layer and in an amorphous phase;
a third layer above the second layer and in a polycrystalline phase; and
a fourth layer above the third layer and in a nano-crystalline phase; and
a pad layer above the barrier layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a material of the second layer is substantially the same as a material of the third layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein a material of the first layer is substantially the same as a material of the fourth layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the third layer is greater than a thickness of the fourth layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of thicknesses of the first layer, the second layer, and the third layer is in a range of about 1.2:1:8.5 to about 1.3:1:9.5.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a sum of thicknesses of the first layer, the second layer, and the third layer is in a range of about 208 angstrom and about 242 angstrom.

### Claim 7

A semiconductor structure comprising:
a multi-level interconnect structure;
a passivation layer above the multi-level interconnect structure;
a pad layer partially in the passivation layer and above the multi-level interconnect structure; and
a barrier layer between the multi-level interconnect structure and the pad layer, wherein the barrier layer comprises:
a first tantalum-containing layer;
a second tantalum-containing layer above the first tantalum-containing layer; and
a third tantalum-containing layer above the second tantalum-containing layer, wherein the first tantalum-containing layer and the third tantalum-containing layer have nitrogen concentrations higher than that of the second tantalum-containing layer, and threading dislocation defects in the first tantalum-containing layer are misaligned with threading dislocation defects of the third tantalum-containing layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein a metal percentage of the second tantalum-containing layer is higher than a metal percentage of the first tantalum-containing layer.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the second tantalum-containing layer is a substantially pure metal layer.

### Claim 10 (depends on 7)

The semiconductor structure of claim 7, wherein the second tantalum-containing layer is free from nitrogen.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the second tantalum-containing layer is in a nano-crystalline phase.

### Claim 12 (depends on 7)

The semiconductor structure of claim 7, wherein the first tantalum-containing layer is in a polycrystalline phase.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, further comprising a fourth tantalum-containing layer between the second tantalum-containing layer and the third tantalum-containing layer, wherein a ratio of a thickness of the fourth tantalum-containing layer to a thickness of the third tantalum-containing layer is in a range of about 0.094 to about 0.129.

### Claim 14 (depends on 7)

The semiconductor structure of claim 7, wherein the first tantalum-containing layer is in contact with the second tantalum-containing layer.

### Claim 15 (depends on 7)

The semiconductor structure of claim 7, wherein a thickness of the second tantalum-containing layer is less than a thickness of the third tantalum-containing layer.

### Claim 16

A semiconductor structure comprising:
an inter-metal dielectric layer;
a conductive line embedded in the inter-metal dielectric layer;
a passivation layer over the inter-metal dielectric layer and covering a portion of the conductive line;
a pad layer partially embedded in the passivation layer and over the conductive line; and
a barrier layer between the pad layer and the conductive line, wherein the barrier layer comprises:
a first layer in a nano-crystalline phase;
a second layer above the first layer and in a poly-crystalline phase;
a third layer above the second layer and in the nano-crystalline phase; and
a fourth layer above the third layer and in the poly-crystalline phase.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein a thickness of the second layer is greater than a thickness of the fourth layer.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the second layer has a nitrogen concentration higher than that of the first layer.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, further comprising a fifth layer in an amorphous phase and between the first layer and the second layer.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein the fifth layer has a nitrogen concentration higher than that of the first layer.