# US 11,908,796 B2 · Semiconductor device and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,796 B2 - Document ID: US11908796B2 - Status: Granted - Kind: B2 - Application number: 17/460,336 - Filed: 2021-08-30 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chih-Yu Tseng; Wei-Lun Hu - Web page: https://patentgrep.com/patent/US11908796B2 ## CPC - H10W 20/43: Layouts of interconnections - H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation} - H10W 20/063: {by forming conductive members before forming protective insulating material} - H10W 20/0633: {using subtractive patterning of the conductive members} - H10W 20/092: {by smoothing the dielectric parts} - H10W 20/098: {by filling between adjacent conductive parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The substrate includes a dense region and an isolation region. The first metal layer is disposed over the substrate and includes a first metal pattern and a second metal pattern. The first metal pattern is located in the dense region. There is at least one slot in the first metal pattern. The second metal pattern is located in the isolation region. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate comprising a dense region and an isolation region; a first metal layer disposed over the substrate and comprising: a plurality of first metal patterns located in the dense region, wherein the first metal patterns are separated from each other, and at least one of the first metal patterns includes at least one dielectric portion therein; and a second metal pattern located in the isolation region; a dielectric layer disposed on the first metal layer; and a second metal layer disposed on the dielectric layer, comprising: a third metal pattern located in the dense region; and a fourth metal pattern located in the isolation region, wherein a thickness of the third metal pattern is less than a thickness of the fourth metal pattern. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the at least one dielectric portion is integrally formed with the dielectric layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the at least one dielectric portion penetrates through the at least one of the first metal patterns. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first metal patterns and the second metal pattern are separated from each other. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the at least one of the first metal patterns comprises a first metal portion surrounding the at least one dielectric portion and the second metal pattern comprises a second metal portion, a ratio of a top view area of the first metal portion to a top view area of the dense region is greater than a ratio of a top view area of the second metal portion to a top view area of the isolation region. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the dielectric layer on the first metal patterns is greater than a thickness of the dielectric layer on the second metal pattern. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a bottom surface of the third metal pattern is higher than a bottom surface of the fourth metal pattern. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: a passivation layer disposed between the third metal pattern and the fourth metal pattern. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein a top surface of the passivation layer is substantially flush with a top surface of the third metal pattern and a top surface of the fourth metal pattern. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein the passivation layer has an inclined sidewall extending between a bottom surface of the third metal and a bottom surface of the fourth metal. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein a top surface of the third metal pattern is substantially flush with a top surface of the fourth metal pattern. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the third metal pattern continuously extends over the first metal patterns. ### Claim 13 A semiconductor device, comprising: a substrate comprising a dense region and an isolation region; a first metal layer disposed over the substrate and comprising: a plurality of first metal patterns located in the dense region, wherein the first metal patterns are separated from each other; and at least one second metal pattern located in the isolation region; a dielectric layer disposed on the first metal layer, wherein the dielectric layer has a first top surface in the dense region and a second top surface in the isolation region, and the first top surface is higher than the second top surface, and a portion of the dielectric layer is disposed in at least one of the first metal patterns; and a second metal layer disposed on the dielectric layer and comprising: a third metal pattern located on the first top surface; and a fourth metal pattern located on the second top surface, wherein a top surface of the third metal pattern is substantially flush with a top surface of the fourth metal pattern, and the second metal layer is in direct contact with the dielectric layer. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the at least one second metal pattern comprises a plurality of second metal patterns, and the dielectric layer is continuously disposed in the at least one of the first metal patterns, disposed between the first metal patterns and disposed between the second metal patterns. ### Claim 15 A method of fabricating a semiconductor device, comprising: providing a substrate, wherein the substrate comprising a dense region and an isolation region; forming a first metal layer over the substrate, wherein the first metal layer comprises: a plurality of first metal patterns located in the dense region, wherein the first metal patterns are separated from each other, and at least one of the first metal patterns comprises at least one slot; and a second metal pattern located in the isolation region; forming a dielectric layer on the first metal layer, to fill the at least one slot, such that the at least one of the first metal patterns comprises at least one dielectric portion therein; and forming a second metal layer on the dielectric layer, the second metal layer comprising: a third metal pattern located in the dense region; and a fourth metal pattern located in the isolation region, wherein a thickness of the third metal pattern is less than a thickness of the fourth metal pattern. ### Claim 16 (depends on 15) The method of fabricating the semiconductor device according to claim 15, wherein a method of forming the first metal layer comprises: forming a first metal material layer over the substrate; patterning the first metal material layer to form the first metal layer. ### Claim 17 (depends on 15) The method of fabricating the semiconductor device according to claim 15, further comprising: performing a chemical mechanical polishing process on the dielectric layer. ### Claim 18 (depends on 15) The method of fabricating the semiconductor device according to claim 15, wherein the dielectric layer has a first top surface in the dense region and a second top surface in the isolation region, and the first top surface is higher than the second top surface, the third metal pattern is located on the first top surface and the fourth metal pattern is located on the second top surface. ### Claim 19 (depends on 18) The method of fabricating the semiconductor device according to claim 18, wherein a method of forming the second metal layer comprises: forming a second metal material layer on the dielectric layer; patterning the second metal material layer to form the second metal layer; forming a passivation material layer on the third metal pattern and the fourth metal pattern; performing a first chemical mechanical polishing process on the passivation material layer; after performing the first chemical mechanical polishing process, performing an etch back process on the passivation material layer to expose a top surface of the third metal pattern, wherein after performing the etch back process, the passivation material layer remains on a top surface of the fourth metal pattern; and after performing the etch back process, performing a second chemical mechanical polishing process on the third metal pattern and the passivation material layer to expose the top surface of the fourth metal pattern and to form a passivation layer, wherein the passivation layer is disposed between the third metal pattern and the fourth metal pattern. ### Claim 20 (depends on 19) The method of fabricating the semiconductor device according to claim 19, wherein the second chemical mechanical polishing process is further performed on the fourth metal pattern.