# US 11,908,795 B2 · Package structures and method of forming the same

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- Number: US 11,908,795 B2
- Document ID: US11908795B2
- Status: Granted
- Kind: B2
- Application number: 17/322,004
- Filed: 2021-05-17
- Published: 2021-09-02
- Granted: 2024-02-20
- Earliest claimed: 2015-08-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; An-Jhih Su
- Web page: https://patentgrep.com/patent/US11908795B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

## Claims

### Claim 1

A structure comprising:
a first integrated circuit die, the first integrated circuit die comprising active devices;
a second integrated circuit die over the first integrated circuit die, the second integrated circuit die comprising active devices and a front side and a backside, the front side of the second integrated circuit die having die connectors, the backside of the second integrated circuit die being free from die connectors, the backside of the second integrated circuit die being coupled to and facing a front side of the first integrated circuit die;
an encapsulant laterally surrounding the second integrated circuit die;
a first conductive via extending through the encapsulant, the first conductive via being electrically coupled to the first integrated circuit die, the first conductive via comprising:
a first portion over the first integrated circuit die, the first portion having a first width, the first width being measured in a first direction, the first direction being parallel to a major surface of the first integrated circuit die; and
a second portion over the first portion, the second portion having a second width, the second width being measured in the first direction, the second width being less than the first width.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising:
a redistribution structure on top surfaces of the first conductive via, the encapsulant, and the second integrated circuit die.

### Claim 3 (depends on 2)

The structure of claim 2, wherein the redistribution structure comprises:
a dielectric layer on the top surfaces of the first conductive via, the encapsulant, and the second integrated circuit die; and
a metallization pattern having a via portion and a line portion, the via portion of the metallization pattern extending through the dielectric layer to contact the first conductive via, the line portion of the metallization pattern extending along a surface of the dielectric layer.

### Claim 4 (depends on 3)

The structure of claim 3, wherein at least one sidewall of the metallization pattern directly overlies the first conductive via.

### Claim 5 (depends on 1)

The structure of claim 1 further comprising:
a dielectric layer on the top surfaces of the first conductive via, the encapsulant, and the second integrated circuit die;
a first via in the dielectric layer and on the first conductive via;
a second conductive via over the first integrated circuit die and adjacent the first conductive via;
a second via in the dielectric layer and on the second conductive via;
a first metallization pattern on the first via and the dielectric layer;
a second metallization pattern on the second via and the dielectric layer; and
a third metallization pattern on the dielectric layer between the first metallization pattern and the second metallization pattern, the third metallization pattern being spaced apart from the first and second metallization patterns.

### Claim 6 (depends on 5)

The structure of claim 5 further comprising:
a fourth metallization pattern on the dielectric layer, the fourth metallization pattern being disposed between the first metallization pattern and the second metallization pattern, the fourth metallization pattern being spaced apart from the first metallization pattern, the second metallization pattern, and the third metallization pattern.

### Claim 7 (depends on 1)

The structure of claim 1, wherein top surfaces of the first conductive via, the encapsulant, and the second integrated circuit die are level.

### Claim 8 (depends on 2)

The structure of claim 2, wherein the first integrated circuit die is electrically coupled to the second integrated circuit die through the first conductive via and the redistribution structure.

### Claim 9

A structure comprising:
a first via and a second via over and electrically coupled to a first die;
a second die over the first die, a front side of the second die facing away from the first die;
a first encapsulant encapsulating the first die, the second die, the first via, and the second via;
a first redistribution structure over the first die, the second die, the first via, the second via, and the first encapsulant, the first redistribution structure comprising:
a third via on the first via;
a fourth via on the second via;
a first metallization pattern on the third via, a first sidewall of the first metallization pattern directly overlying the first via; and
a second metallization pattern on the fourth via, a second sidewall of the second metallization pattern directly overlying the second via, wherein the first die is electrically coupled to the second die through the first via and at least a portion of the first redistribution structure.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the first redistribution structure further comprises:
a first dielectric layer over the first via and the second die, the third and fourth vias extending through the first dielectric layer.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the first metallization pattern and the second metallization pattern are on a top surface of the first dielectric layer.

### Claim 12 (depends on 9)

The structure of claim 9, wherein the first via further comprises:
a first portion of the first via having a first width, the first width being measured in a first plane, the first plane being parallel to a major surface of the first die; and
a second portion of the first via on the first portion of the first via, the second portion having a second width, the second width being measured in the first plane.

### Claim 13 (depends on 12)

The structure of claim 12, wherein a bottom surface of the first portion of the first via is coplanar with a back side surface of the second die, and wherein a top surface of the second portion of the first via is coplanar with an active surface of the second die.

### Claim 14 (depends on 9)

The structure of claim 9, wherein a back side of the second die is proximate an active side of the first die.

### Claim 15 (depends on 9)

The structure of claim 9, wherein inner sidewalls of the first via and the second via are separated by a first distance.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the first sidewall of the first metallization pattern and the second sidewall of the second metallization pattern are separated by a second distance, the second distance being greater than the first distance.

### Claim 17

A structure comprising:
a first through via over and electrically coupled to a first die;
a second die over the first die;
an encapsulant on sidewalls of the first die, the second die, and the first through via;
a first redistribution structure over the second die, the first through via, and the encapsulant, the first redistribution structure comprising:
a dielectric layer over the second die, the first through via, and the encapsulant;
a first via in the dielectric layer and on the first through via; and
a first metallization pattern on the first via, a sidewall of the first metallization pattern directly overlying the first through via,
wherein the first die is electrically coupled to the second die through the first through via and at least a portion of the first redistribution structure.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the first through via comprises:
a first portion of the first through via having a first width, the first width being measured in a first direction, the first direction being parallel to a major surface of the first die; and
a second portion of the first through via on the first portion of the through via, the second portion having a second width, the second width being measured in the first direction.

### Claim 19 (depends on 17)

The structure of claim 17 further comprising:
a second through via over and electrically coupled to a first die, the second through via extending through the encapsulant, wherein the first redistribution structure further comprises:
a second via in the dielectric layer and on the second through via; and
a second metallization pattern on the second via, a sidewall of the second metallization pattern directly overlying the second through via.

### Claim 20 (depends on 19)

The structure of claim 19 further comprising:
a third metallization pattern between the first and second metallization patterns, the third metallization pattern being at a same level as the first metallization pattern and the second metallization pattern.