# US 11,908,793 B2 · Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,793 B2 - Document ID: US11908793B2 - Status: Granted - Kind: B2 - Application number: 17/716,937 - Filed: 2022-04-08 - Published: 2022-07-21 - Granted: 2024-02-20 - Earliest claimed: 2019-04-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jiun Hann Sir; Poh Boon Khoo; Eng Huat Goh; Amruthavalli Pallavi Alur; Debendra Mallik - Web page: https://patentgrep.com/patent/US11908793B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/685: comprising multiple insulating layers - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/63: Vias, e.g. via plugs - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/07254: {changes in dispositions} - H10W 72/247: {Dispositions of multiple bumps} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate. ## Claims ### Claim 1 An integrated-circuit device package, comprising: an interconnect bridge in a dielectric layer, the interconnect bridge comprising traces, and the interconnect bridge having a top side and a bottom side opposite the top side, a first side between the top side and the bottom side, and a second side between the top side and the bottom side; a first via and a second via in the dielectric layer, the first via and the second via laterally adjacent to the first side of the interconnect bridge; a third via and a fourth via in the dielectric layer, the third via and the fourth via laterally adjacent to the second side of the interconnect bridge; a first integrated circuit chip coupled to the top side of the interconnect bridge, the first integrated circuit chip electrically coupled to the first via and the second via; a second integrated circuit chip having a top side and a bottom side, the bottom side of the second integrated circuit chip coupled to the top side of the interconnect bridge, the second integrated circuit chip electrically coupled to the third via and the fourth via; a third integrated circuit chip coupled to the top side of the second integrated circuit chip; and a plurality of bumps beneath interconnect bridge, the plurality of bumps within a footprint of the first side and the second side of the interconnect bridge. ### Claim 2 (depends on 1) The integrated-circuit device package of claim 1, wherein the first via, the second via, the third via, and the fourth via each have a lowermost surface that extends at least to the bottom side of the interconnect bridge. ### Claim 3 (depends on 1) The integrated-circuit device package of claim 1, wherein the first via, the second via, the third via, and the fourth via each have a lowermost surface that extends below the bottom side of the interconnect bridge. ### Claim 4 (depends on 1) The integrated-circuit device package of claim 1, wherein the first via, the second via, the third via, and the fourth via each have an uppermost surface above an uppermost surface of the interconnect bridge. ### Claim 5 (depends on 1) The integrated-circuit device package of claim 1, further comprising: a fourth integrated circuit chip coupled to the top side of the second integrated circuit chip. ### Claim 6 (depends on 3) The integrated-circuit device package of claim 3, further comprising: a fifth integrated circuit chip coupled to the top side of the second integrated circuit chip. ### Claim 7 (depends on 6) The integrated-circuit device package of claim 6, wherein the fourth integrated circuit chip is laterally adjacent to the third integrated circuit chip, and the fifth integrated circuit chip is laterally adjacent to the fourth integrated circuit chip. ### Claim 8 (depends on 6) The integrated-circuit device package of claim 6, wherein each of the third integrated circuit chip, the fourth integrated circuit chip, and the fifth integrated circuit chip is directly attached to the top side of the second integrated circuit chip. ### Claim 9 (depends on 6) The integrated-circuit device package of claim 6, wherein the second integrated circuit chip comprises a plurality of through silicon vias (TSVs) therein. ### Claim 10 (depends on 1) The integrated-circuit device package of claim 1, further comprising: a sixth integrated circuit chip coupled to a top side of the first integrated circuit chip. ### Claim 11 (depends on 1) The integrated-circuit device package of claim 1, wherein the interconnect bridge is in direct contact with the dielectric layer, and wherein each of the first, second, third and fourth vias is in direct contact with the dielectric layer. ### Claim 12 (depends on 1) The integrated-circuit device package of claim 1, wherein the first integrated circuit chip is attached to the top side of the interconnect bridge by a plurality of pillars of the interconnect bridge and by a plurality of bonding pads of the first integrated circuit chip. ### Claim 13 (depends on 1) The integrated-circuit device package of claim 1, further comprising: a heat slug coupled to the bottom side of the interconnect bridge. ### Claim 14 (depends on 13) The integrated-circuit device package of claim 13, wherein the heat slug is attached to the bottom side of the interconnect bridge by a die attach film. ### Claim 15 (depends on 13) The integrated-circuit device package of claim 13, wherein the heat slug is a VSS layer. ### Claim 16 An integrated-circuit device package, comprising: a silicon bridge in a dielectric layer, the silicon bridge comprising traces, and the silicon bridge having a top side and a bottom side opposite the top side, a first side between the top side and the bottom side, and a second side between the top side and the bottom side; a first via in the dielectric layer, the first via laterally adjacent to the first side of the silicon bridge; a second via in the dielectric layer, the second via laterally adjacent to the second side of the silicon bridge; a first integrated circuit chip coupled to the top side of the silicon bridge, the first integrated circuit chip electrically coupled to the first via; a second integrated circuit chip having a top side and a bottom side, the bottom side of the second integrated circuit chip coupled to the top side of the silicon bridge, the second integrated circuit chip electrically coupled to the second via; a third integrated circuit chip coupled to the top side of the second integrated circuit chip; and a plurality of bumps beneath silicon bridge, the plurality of bumps within a footprint of the first side and the second side of the silicon bridge. ### Claim 17 (depends on 16) The integrated-circuit device package of claim 16, wherein the first via and the second via each have an uppermost surface above an uppermost surface of the silicon bridge. ### Claim 18 (depends on 16) The integrated-circuit device package of claim 16, wherein the first integrated circuit chip is attached to the top side of the silicon bridge by a pillar of the silicon bridge and by a bonding pad of the first integrated circuit chip. ### Claim 19 (depends on 16) The integrated-circuit device package of claim 16, further comprising: a heat slug coupled to the bottom side of the silicon bridge. ### Claim 20 (depends on 19) The integrated-circuit device package of claim 19, wherein the heat slug is attached to the bottom side of the silicon bridge by a die attach film. ### Claim 21 (depends on 19) The integrated-circuit device package of claim 19, wherein the heat slug is a VSS layer. ### Claim 22 (depends on 16) The integrated-circuit device package of claim 16, further comprising: a fourth integrated circuit chip coupled to the top side of the second integrated circuit chip; and a fifth integrated circuit chip coupled to the top side of the second integrated circuit chip.