# US 11,908,792 B2 · Semiconductor device comprising cap layer over dielectric layer and method of manufacture

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- Number: US 11,908,792 B2
- Document ID: US11908792B2
- Status: Granted
- Kind: B2
- Application number: 17/536,324
- Filed: 2021-11-29
- Published: 2022-03-17
- Granted: 2024-02-20
- Earliest claimed: 2019-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Shao-Kuan Lee; Hai-Ching Chen; Hsin-Yen Huang; Shau-Lin Shue; Cheng-Chin Lee
- Web page: https://patentgrep.com/patent/US11908792B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a first conductive feature;
a second conductive feature;
a first dielectric layer positioned between the first conductive feature and the second conductive feature;
an etch stop layer over the first dielectric layer;
a cap layer over the first conductive feature, the second conductive feature, and the etch stop layer, wherein the cap layer is adjacent a first sidewall of the etch stop layer and in direct contact with the first conductive feature; and
a contact overlying a portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature, wherein:
the contact is separated from the portion of the first dielectric layer by the etch stop layer, and
the contact is in direct contact with a top surface of the etch stop layer and electrically coupled to the second conductive feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the contact is in direct contact with a sidewall of the cap layer and a second sidewall of the etch stop layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the contact is in direct contact with a sidewall of the cap layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the cap layer is in direct contact with the first sidewall of the etch stop layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, comprising:
a second dielectric layer over the cap layer, wherein a sidewall of the second dielectric layer is adjacent a sidewall of the cap layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the sidewall of the second dielectric layer is in direct contact with the sidewall of the cap layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, comprising:
an encapsulation layer between the first dielectric layer and the second conductive feature.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the etch stop layer overlies a top surface of the encapsulation layer.

### Claim 9

A semiconductor device, comprising:
a first conductive feature;
a second conductive feature;
a first dielectric layer positioned between the first conductive feature and the second conductive feature;
an etch stop layer over the first dielectric layer;
a cap layer over the first conductive feature, the second conductive feature, and the etch stop layer, wherein the cap layer is adjacent a first sidewall of the etch stop layer and extends from a bottommost surface of the etch stop layer to a topmost surface of the etch stop layer along the first sidewall of the etch stop layer; and
a contact overlying a portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature, wherein:
the contact is separated from the portion of the first dielectric layer by the etch stop layer, and
the contact is in direct contact with a sidewall of the cap layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the contact is in direct contact with a second sidewall of the etch stop layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, comprising:
an encapsulation layer between the first dielectric layer and the second conductive feature.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the etch stop layer overlies a top surface of the encapsulation layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, comprising:
a glue layer under the second conductive feature.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, comprising:
an encapsulation layer between the first dielectric layer and the second conductive feature, wherein a sidewall of the encapsulation layer is adjacent a sidewall of the glue layer.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, comprising:
a second dielectric layer, wherein a sidewall of the second dielectric layer is adjacent a sidewall of the cap layer.

### Claim 16

A semiconductor device, comprising:
a first conductive feature;
a second conductive feature;
a first dielectric layer positioned between the first conductive feature and the second conductive feature;
a cap layer over the first conductive feature, the second conductive feature, and the first dielectric layer, wherein the cap layer directly contacts the second conductive feature; and
a contact overlying a portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature, wherein:
the contact contacts a sidewall of the cap layer, and
the contact is electrically coupled to the second conductive feature.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, comprising:
an etch stop layer, wherein the cap layer is spaced apart from the portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature by the etch stop layer.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, comprising:
an etch stop layer, wherein the contact directly contacts a sidewall and a top surface of the etch stop layer.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein an air gap is defined in the portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the cap layer is spaced apart from the first dielectric layer.