# US 11,908,791 B2 · Partial subtractive supervia enabling hyper-scaling

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- Number: US 11,908,791 B2
- Document ID: US11908791B2
- Status: Granted
- Kind: B2
- Application number: 17/532,310
- Filed: 2021-11-22
- Published: 2023-05-25
- Granted: 2024-02-20
- Earliest claimed: 2021-11-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Sagarika Mukesh; Nicholas Anthony Lanzillo
- Web page: https://patentgrep.com/patent/US11908791B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.

## Claims

### Claim 1

A semiconductor device comprising:
an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration; and
a lower section of the supervia, formed via damascene processing, that defines a generally cone-shaped configuration,
wherein the supervia connects non-adjacent interconnect wiring.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a distal end of the lower section of the supervia is non-obtuse.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a distal end of the lower section of the supervia is generally flat.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a maximum width of the lower section of the supervia is equal to a maximum width of the upper section of the supervia.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.

### Claim 7

A semiconductor device comprising:
an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration; and
a lower section of the supervia formed, via damascene processing, that defines a generally cone-shaped configuration,
wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the supervia connects non-adjacent interconnect wiring.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein a distal end of the lower section of the supervia is non-obtuse.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein a distal end of the lower section of the supervia is generally flat.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.

### Claim 12

A method comprising:
forming an upper section of a supervia via subtractive etching to define a generally cone-shaped configuration of the upper section;
forming a lower section of the supervia via damascene processing to define a generally cone-shaped configuration of the lower section; and
enabling the supervia to connect non-adjacent interconnect wiring.

### Claim 13 (depends on 12)

The method of claim 12, wherein a distal end of the lower section of the supervia is generally flat.

### Claim 14 (depends on 12)

The method of claim 12, wherein a distal end of the lower section of the supervia is non-obtuse.

### Claim 15 (depends on 12)

The method of claim 12, wherein the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.

### Claim 16 (depends on 12)

The method of claim 12, wherein a maximum width of the lower section of the supervia is equal to a maximum width of the upper section of the supervia.

### Claim 17 (depends on 12)

The method of claim 12, wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.