# US 11,908,786 B2 · Wiring structure

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- Number: US 11,908,786 B2
- Document ID: US11908786B2
- Status: Granted
- Kind: B2
- Application number: 17/676,091
- Filed: 2022-02-18
- Published: 2023-08-24
- Granted: 2024-02-20
- Earliest claimed: 2022-02-18
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Ting Wei Hsu
- Web page: https://patentgrep.com/patent/US11908786B2

## CPC

- H10W 40/10: Arrangements for heating
- H10W 70/65: Shapes or dispositions of interconnections
- G01R 31/2818: {using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors (G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266)}
- H05K 1/0201: {Thermal arrangements, e.g. for cooling, heating or preventing overheating}
- H05K 1/0209: {External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings}
- H05K 1/0268: {for electrical inspection or testing}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/685: comprising multiple insulating layers
- G01R 31/2812: {Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance (of connections G01R31/66)}
- G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.

## Claims

### Claim 1

A wiring structure, comprising:
a test pattern layer, comprising:
a plurality of test circuit patterns intersected with each other at an intersection portion; and
a heat dissipating structure disposed adjacent to the plurality of test circuit patterns, and configured to reduce temperature rise of the plurality of test circuit patterns when a power is applied to the plurality of test circuit patterns, wherein the heat dissipating structure is spaced apart from the intersection portion.

### Claim 2 (depends on 1)

The wiring structure of claim 1, wherein the heat dissipating structure is disposed along at least one of the plurality of test circuit patterns.

### Claim 3 (depends on 2)

The wiring structure of claim 2, wherein the heat dissipating structure includes a pattern extending from the at least one of the plurality of test circuit patterns.

### Claim 4 (depends on 1)

The wiring structure of claim 1, wherein at least one of the plurality of test circuit patterns includes an end portion, and the heat dissipating structure is closer to the end portion than the intersection portion is.

### Claim 5 (depends on 1)

The wiring structure of claim 1, wherein the heat dissipating structure includes a pattern tapered toward the intersection portion.

### Claim 6 (depends on 1)

The wiring structure of claim 1, further comprising:
a dielectric layer, wherein the plurality of test circuit patterns is disposed on the dielectric layer; and
a circuit pattern layer disposed on the dielectric layer and spaced apart from the test pattern layer, wherein a width of one of the plurality of test circuit patterns is substantially equal to a width of a conductive line of the circuit pattern layer.

### Claim 7 (depends on 6)

The wiring structure of claim 6, wherein the test pattern layer further includes a second test circuit pattern intersected with the one of the plurality of test circuit patterns at an intersection portion, and a width of the intersection portion is substantially equal to the width of the conductive line of the circuit pattern layer.

### Claim 8 (depends on 7)

The wiring structure of claim 7, wherein in a top view, the one of the plurality of test circuit patterns is nonparallel with the second test circuit pattern.

### Claim 9

A wiring structure, comprising:
a dielectric layer;
a circuit pattern layer disposed on the dielectric layer; and
a test pattern layer disposed on the dielectric layer, and spaced apart from the circuit pattern layer, and comprising:
a test circuit pattern; and
an etching buffer layer disposed adjacent to the test circuit pattern, and configured to reduce a delamination between the test circuit pattern and the dielectric layer.

### Claim 10 (depends on 9)

The wiring structure of claim 9, wherein a width of a portion of the etching buffer layer is greater than a width of a portion of the test circuit pattern.

### Claim 11 (depends on 10)

The wiring structure of claim 10, wherein the test pattern layer includes a plurality of test circuit patterns intersected with each other at an intersection portion, one of the test circuit patterns includes an end portion, and the etching buffer layer is closer to the intersection portion than the end portion is.

### Claim 12 (depends on 11)

The wiring structure of claim 11, wherein a width of the intersection portion is substantially equal to a width of a conductive line of the circuit pattern layer.

### Claim 13 (depends on 9)

The wiring structure of claim 9, wherein a thickness of the etching buffer layer is substantially equal to a thickness of the test circuit pattern.

### Claim 14 (depends on 9)

The wiring structure of claim 9, wherein a seed layer is disposed between the test circuit pattern and the dielectric layer.

### Claim 15 (depends on 14)

The wiring structure of claim 14, wherein a width of the seed layer is less than a width of the test circuit pattern.

### Claim 16

A wiring structure, comprising:
a dielectric layer having a first region and a second region;
a circuit pattern layer disposed in the first region; and
a test pattern layer disposed in the second region, and comprising:
at least two test circuit patterns intersected with each other at an intersection portion; and
a heat dissipating layer disposed around the intersection portion.

### Claim 17 (depends on 16)

The wiring structure of claim 16, wherein the heat dissipating layer includes at least two heat dissipating patterns connected to the at least two test circuit patterns, respectively.

### Claim 18 (depends on 17)

The wiring structure of claim 17, wherein the heat dissipating layer further includes at least one second heat dissipating pattern spaced apart from the at least two the test circuit patterns, and the second heat dissipating pattern is disposed between the test circuit patterns.

### Claim 19 (depends on 18)

The wiring structure of claim 18, wherein the at least one second heat dissipating pattern includes a plurality of second heat dissipating patterns disposed around the intersection portion.