# US 11,908,785 B2 · Semiconductor device and methods of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,785 B2 - Document ID: US11908785B2 - Status: Granted - Kind: B2 - Application number: 17/238,286 - Filed: 2021-04-23 - Published: 2021-11-25 - Granted: 2024-02-20 - Earliest claimed: 2020-05-19 - Assignees: Panasonic Intellectual Property Management Co., Ltd. - Applicants: Panasonic Intellectual Property Management Co., Ltd. - Inventors: Takeru Tamari; Daisuke Sakurai; Kiyokazu Itoi - Web page: https://patentgrep.com/patent/US11908785B2 ## CPC - G01B 7/18: {using change in resistance} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - G01B 7/20: {formed by printed-circuit technique} - H10F 39/811: {Interconnections} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/218: {in silicon-on-insulator [SOI] wafers} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - G01B: MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A semiconductor device includes: a first board that has a first end surface and a second end surface opposite to the first end surface; a second board that is attached to the second end surface of the first board; a plurality of first electrodes that are provided on the first end surface; a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board; an internal wiring that is provided inside the first board and electrically coupled to the second electrode; a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and a strain sensor that is provided inside the first board and measures a strain generated in the first board, in which a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board. ## Claims ### Claim 1 A semiconductor device comprising: a first board that has a first end surface and a second end surface opposite to the first end surface; a second board that is attached to the second end surface of the first board; a plurality of first electrodes that are provided on the first end surface; a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board; an internal wiring that is provided inside the first board and electrically coupled to the second electrode; a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and a strain sensor that is provided inside the first board and measures a strain generated in the first board, wherein a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board, the first board includes a plurality of layers that are laminated, the linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the internal wiring, the strain sensor is provided inside a strain sensor forming layer, the strain sensor forming layer including two insulating layers and a semiconductor layer that forms the strain sensor, the semiconductor layer being provided between the two insulating layers, and the plurality of third electrodes pass through one of the two insulating layers. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the strain sensor is provided between the plurality of third electrodes arranged apart from each other in a direction orthogonal to a laminating direction in which the first board and the second board are laminated. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the strain sensor is adjacent to and electrically coupled to one of the plurality of third electrodes in a direct manner. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the strain sensor is adjacent to and electrically coupled to one of the plurality of third electrodes through internal wirings and micro vias arranged in the laminating direction. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the second electrode overlaps with the third electrode in a laminating direction in which the first board and the second board are laminated, and the strain sensor is provided adjacent to the third electrode. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the plurality of second electrodes overlap with the third electrode in the laminating direction. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor layer that forms the strain sensor is made of single crystal silicon. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the strain sensor is formed of an n-type semiconductor. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the strain sensor has a shape extending along a crystal orientation of the semiconductor layer that forms the strain sensor. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the shape of the strain sensor in a plan view in a laminating direction in which the first board and the second board are laminated is rectangular. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the strain sensor that is rectangular is disposed such that a longitudinal side portion of the strain sensor is parallel to the crystal orientation. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein a circuit other than the strain sensor is formed on the semiconductor layer on which the strain sensor is formed. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein the first board has holes, in which the third electrodes are disposed, and an insulating film formed on an inner peripheral surface of each of the holes. ### Claim 14 (depends on 1) The semiconductor device of claim 1, wherein each of the third electrodes includes a film-shaped electrode material formed at a bottom portion of a hole in which the third electrode is disposed. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein the plurality of third electrodes include an electrode to which the strain sensor is coupled and an electrode to which a circuit other than the strain sensor is coupled. ### Claim 16 (depends on 1) The semiconductor device of claim 1, wherein the plurality of third electrodes are provided inside the plurality of layers of the first board. ### Claim 17 (depends on 1) The semiconductor device of claim 1, wherein the plurality of third electrodes pass through the strain sensor forming layer.