# US 11,908,783 B2 · Wiring substrate, semiconductor package having the wiring substrate, and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,783 B2 - Document ID: US11908783B2 - Status: Granted - Kind: B2 - Application number: 17/507,653 - Filed: 2021-10-21 - Published: 2022-02-10 - Granted: 2024-02-20 - Earliest claimed: 2015-12-11 - Assignees: Amkor Technology Singapore Holding Pte. Ltd. - Applicants: Amkor Technology Singapore Holding Pte. Ltd. - Inventors: Naoki Hayashi - Web page: https://patentgrep.com/patent/US11908783B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/095: {of vias therein} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/073: {of die-attach connectors} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 90/00: Package configurations - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via. ## Claims ### Claim 1 A semiconductor package, comprising: a first power device having a first surface, a second surface opposite to the first surface, and a first terminal adjacent to the first surface of the first power device; a second power device having a first surface, a second surface opposite to the first surface, and a second terminal adjacent to the first surface of the second power device; a control device having a first surface, a second surface opposite to the first surface, and control device terminals adjacent to the first surface of the control device; a first lower wiring adjacent to the second surface of the first power device; a second lower wiring adjacent to the second surface of the second power device; a third lower wiring adjacent to the second surface of the control device; a first insulating layer covering the first power device, the second power device, the control device, the first lower wiring, the second lower wiring, and the third lower wiring, the first insulating layer comprising first openings extending from a first surface of the first insulating layer to the first terminal, the second terminal, and the control device terminals; a first conductive layer over the first terminal and the second terminal but not over the control device terminals; a second conductive layer over the first terminal, the second terminal, and the control device terminals, wherein: the second conductive layer is within the first openings; the second conductive layer is interposed between the first terminal and the first conductive layer and interposed between the second terminal and the first conductive layer; and a first portion of the first conductive layer and a first portion of the second conductive layer are coupled to the first terminal and the second lower wiring through one of the first openings in the first insulating layer; and a second insulating layer covering the first conductive layer and the second conductive layer. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein: the first power device further comprises a first control terminal; the second power device further comprises a second control terminal; and the first control terminal and the second control terminal are not covered by the first conductive layer. ### Claim 3 (depends on 2) The semiconductor package according to claim 2, wherein: the second conductive layer couples one of the control device terminals to one or more of the first control terminal or the second control terminal. ### Claim 4 A semiconductor package, comprising: a first power device having a first surface, a second surface opposite to the first surface, a first terminal adjacent to the first surface of the first power device, and a first control terminal; a first lower wiring adjacent to the second surface of the first power device; a first insulating layer covering the first power device, and the first lower wiring, wherein: the first insulating layer comprises first openings extending from a first surface of the first insulating layer to the first terminal; a first conductive layer over the first terminal and but not over the first control terminal; a second conductive layer over the first terminal and the first control terminal; and a second insulating layer; wherein: the second conductive layer is within the first openings; the second conductive layer is interposed between the first terminal and the first conductive layer; the second conductive layer and the first conductive layer are within the second insulating layer; the first conductive layer comprises a first conductive layer top side distal to the second conductive layer; and the second insulating layer overlaps and covers the first conductive layer top side. ### Claim 5 (depends on 4) The semiconductor package according to claim 4, further comprising: a second power device having a first surface, a second surface opposite to the first surface, a second terminal adjacent to the first surface of the second power device, and a second control terminal; and a second lower wiring adjacent to the second surface of the second power device; wherein: the first openings extend from the first surface of the first insulating layer to the second terminal; the first conductive layer is over the second terminal but not over the second control terminal; the second conductive layer is over the second terminal and the second control terminal; and the second conductive layer is interposed between the first conductive layer and the second terminal. ### Claim 6 (depends on 5) The semiconductor package according to claim 5, wherein: a first portion of the first conductive layer and a first portion of the second conductive layer are coupled to the first terminal and the second lower wiring through one of the first openings in the first insulating layer. ### Claim 7 (depends on 6) The semiconductor package according to claim 6, wherein: the second insulating layer comprises second openings extending from a first surface of the second insulating layer to a second portion of the first conductive layer that is over the second power device; and the semiconductor package further comprises an upper wiring within the second openings and coupled to the second portion of the first conductive layer. ### Claim 8 (depends on 7) The semiconductor package according to claim 7, wherein: the second insulating layer is devoid of second openings above the first portion of the first conductive layer. ### Claim 9 (depends on 4) The semiconductor package according to claim 4, further comprising: a control device having a first surface, a second surface opposite to the first surface, and control device terminals adjacent to the first surface of the control device; and a second lower wiring adjacent to the second surface of the control device, wherein: the first openings extend from the first surface of the first insulating layer to the control device terminals; the control device terminals are not covered by the first conductive layer; and the second conductive layer is over the control device terminals. ### Claim 10 (depends on 9) The semiconductor package according to claim 9, wherein: the second conductive layer couples one of the control device terminals to the first control terminal. ### Claim 11 (depends on 9) The semiconductor package according to claim 9, wherein: the second insulating layer comprises second openings extending from a first surface of the second insulating layer to the control device terminals; and the semiconductor package further comprises an upper wiring within the second openings and coupled to the control device terminals. ### Claim 12 (depends on 4) The semiconductor package according to claim 4, further comprising: a metal bonding layer interposed between the first conductive layer and the second conductive layer, wherein: the first control terminal is adjacent to the first surface of the first power device; and the first control terminal is devoid of the metal bonding layer. ### Claim 13 (depends on 4) The semiconductor package according to claim 4, wherein: the first conductive layer is coupled to a second lower wiring through one of the first openings in the first insulating layer. ### Claim 14 (depends on 4) The semiconductor package according to claim 4, wherein: the first conductive layer comprises a first conductive layer bottom side opposite to the first conductive layer top side; the second conductive layer comprises a second conductive layer top side; the first conductive layer bottom side is adjacent to the second conductive layer top side; no portion of the second insulating layer is interposed between the first conductive layer bottom side and the second conductive layer top side; and no portion of the first insulating layer is interposed between the first conductive layer bottom side and the second conductive layer top side. ### Claim 15 A method of making a semiconductor package, comprising: providing a semiconductor device comprising a first terminal and a second terminal; providing a first conductive layer over the second terminal; providing a first insulating layer over the first terminal and the second terminal; providing a second insulating layer over the first terminal; providing a first via that extends through the first insulating layer and the second insulating layer to expose at least a portion of the first terminal; providing a second via that extends through the first conductive layer and the first insulating layer to expose at least a portion of the second terminal; and providing a second conductive layer having a first portion within the first via and having a second portion over the first conductive layer and within the second via, wherein: the first insulating layer is interposed between the first conductive layer and the second terminal and interposed between the second insulating layer and the first terminal; the first portion of the second conductive layer is part of a first wiring route; the second portion of the second conductive layer and the first conductive layer are part of a second wiring route; and the first wiring route is devoid of the first conductive layer. ### Claim 16 (depends on 15) The method according to claim 15, wherein: the second insulating layer is not over the second terminal. ### Claim 17 (depends on 15) The method according to claim 15, wherein: the second portion of the second conductive layer overlaps an upper surface of the first conductive layer; the second portion of the second conductive layer has a first thickness overlapping the upper surface of the first conductive layer and a second thickness in the second via; and the first thickness is less than the second thickness. ### Claim 18 (depends on 17) The method according to claim 17, wherein: the first conductive layer has a third thickness; and the first thickness is less than the third thickness. ### Claim 19 (depends on 15) The method according to claim 15, wherein: the first conductive layer comprises a patterned metal plate. ### Claim 20 (depends on 15) The method according to claim 15, wherein: the first conductive layer and the second conductive layer are different in conductivity from each other.