# US 11,908,782 B2 · Spacers formed on a substrate with etched micro-springs

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- Number: US 11,908,782 B2
- Document ID: US11908782B2
- Status: Granted
- Kind: B2
- Application number: 17/208,332
- Filed: 2021-03-22
- Published: 2022-09-22
- Granted: 2024-02-20
- Earliest claimed: 2021-03-22
- Assignees: Xerox Corporation
- Applicants: Palo Alto Research Center Incorporated
- Inventors: Christopher L. Chua; Qian Wang; Yu Wang; Eugene M. Chow
- Web page: https://patentgrep.com/patent/US11908782B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks}
- H10W 72/01231: {using blanket deposition}
- H10W 72/01253: {by etching}
- H10W 72/072: {of bump connectors}
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07353: {changes in shapes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/261: {Functions other than electrical connecting}
- H10W 72/285: {Alignment aids, e.g. alignment marks}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/354: {comprising polymers}
- H10W 72/381: {Auxiliary members}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic assembly and methods of making the assembly are disclosed. The electronic assembly includes a substrate with an elastic member having an intrinsic stress profile. The elastic member has an anchor portion on the surface of the substrate; and a free end biased away from the substrate via the intrinsic stress profile to form an out of plane structure. The substrate includes one or more spacers on the substrate. The electronic assembly includes a chip comprising contact pads. The out of plane structure on the substrate touches corresponding contact pads on the chip, and the spacers on the substrate touch the chip forming a gap between the substrate and the chip.

## Claims

### Claim 1

A method comprising:
depositing a release layer on a substrate;
depositing an elastic metal on the release layer, the elastic metal having an intrinsic stress profile;
etching through the layer of the elastic metal to form one or more elastic members;
coating a spacer material onto the substrate;
patterning the spacer material to form one or more spacers at least partially surrounding the elastic members, wherein the one or more spacers comprise:
a main structure elongated along a first direction; and
tabs extending from the main structure at an angle to the first direction, the tabs preventing delamination of the main structure; and
undercut etching the release layer to release a free end of the elastic member from the substrate while leaving an anchor portion of each of the elastic members fixed to the substrate, the intrinsic stress profile in the elastic member biasing the free end of the elastic member away from the substrate to form an out of plane structure upon release of the free end.

### Claim 2 (depends on 1)

The method of claim 1, wherein the spacer material is coated above the release layer and wherein portions of the release layer underneath the patterned spacer material remains after undercut etching.

### Claim 3 (depends on 1)

The method of claim 1, wherein the release layer at a region on which the one or more spacers are to be formed is removed prior to applying the spacer material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the elastic metal comprises a MoCr alloy.

### Claim 5 (depends on 1)

The method of claim 1, wherein the spacer material comprises a polymer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the polymer comprises at least one of polyimide, SU8, or benzocyclobutene.

### Claim 7 (depends on 5)

The method of claim 5, further comprising curing the polymer at a temperature of 150 degrees C. or less.

### Claim 8 (depends on 1)

The method of claim 1, wherein the release layer comprises Ti, an alloy of Ti, or, SixOyNz, where x, y, and z are fractional constituents ranging from 0 to 1.

### Claim 9 (depends on 1)

The method of claim 1, further comprising assembling the substrate to a chip such that the one or more spacers contact a surface of the chip, the assembly causing the out of plane structures to touch corresponding contact pads on the chip, the one or more spacers having a thickness that results in a predetermined compression of the out of plane structures.

### Claim 10 (depends on 9)

The method of claim 9, further comprising applying an underfill to flow into a gap between the chip and the substrate such that placement of the spacers prevents the underfill from reaching the contact pads.

### Claim 11 (depends on 10)

The method of claim 10, wherein the one or more spacers partially surround the one or more contact pads in an arrangement with openings, the openings allowing for evacuation of air in a contact pad region.

### Claim 12 (depends on 1)

The method of claim 1, wherein the substrate comprises superconducting circuits or low temperature electronics.

### Claim 13 (depends on 1)

The method of claim 1, wherein a thickness of the spacer is 3 μm or more.

### Claim 14 (depends on 1)

The method of claim 1, wherein the elastic members are arranged in a two-dimensional, areal array.

### Claim 15

A method comprising:
depositing a release layer on a substrate, wherein the substrate comprises superconducting circuits or low temperature electronics that are subject to damage at maximum processing temperatures at or above 150° C., wherein the method is performed at a processing temperature below 150° C.;
depositing an elastic metal on the release layer, the elastic metal having an intrinsic stress profile;
etching through the layer of the elastic metal to form one or more elastic members;
coating a spacer material onto the substrate;
patterning the spacer material to form one or more spacers at least partially surrounding the elastic members, wherein the one or more spacers comprise:
a main structure elongated along a first direction; and
tabs extending from the main structure at an angle to the first direction, the tabs preventing delamination of the main structure; and
undercut etching the release layer to release a free end of the elastic member from the substrate while leaving an anchor portion of each of the elastic members fixed to the substrate, the intrinsic stress profile in the elastic member biasing the free end of the elastic member away from the substrate to form an out of plane structure upon release of the free end.

### Claim 16 (depends on 15)

The method of claim 15, wherein the substrate comprises the superconducting circuits, and wherein the superconducting circuits remain functional below 77 Kelvin.

### Claim 17 (depends on 15)

The method of claim 15, wherein the spacer material comprises a polymer, the method further comprising curing the polymer at the processing temperature below 150° C.