# US 11,908,781 B2 · Semiconductor device package and a method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,781 B2 - Document ID: US11908781B2 - Status: Granted - Kind: B2 - Application number: 17/209,085 - Filed: 2021-03-22 - Published: 2022-09-22 - Granted: 2024-02-20 - Earliest claimed: 2021-03-22 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Wei-Chih Cho; Chun-Hung Yeh; Tsung-Wei Lu - Web page: https://patentgrep.com/patent/US11908781B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/69: Insulating materials thereof - H10W 72/0198: {batch processes} - H10W 74/10: characterised by their shape or disposition - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer. ## Claims ### Claim 1 A semiconductor package structure, comprising: a substrate including a first surface; a first encapsulant covering the first surface of the substrate and including an upper surface and a lateral side surface; a patterned conductive layer extending on the upper surface and the lateral side surface of the first encapsulant; and a first electronic component disposed on the patterned conductive layer; and a second electronic component encapsulated by the first encapsulant and electrically connected to the first electronic component through the substrate and the patterned conductive layer, wherein the substrate includes a second surface opposite to the first surface, wherein the semiconductor package structure further comprises a third electronic component connected to the substrate through the second surface of the substrate, and wherein the third electronic component is electrically connected to the first electronic component through the patterned conductive layer. ### Claim 2 (depends on 1) The semiconductor package structure of claim 1, wherein the first encapsulant includes a lower surface opposite to the upper surface, and wherein the patterned conductive layer includes a first portion disposed on the lateral side surface of the first encapsulant, and the first portion includes a lateral side surface non-perpendicular to the upper surface of the first encapsulant from a front view. ### Claim 3 (depends on 2) The semiconductor package structure of claim 2, wherein a width of the first portion tapers towards the upper surface of the first encapsulant. ### Claim 4 (depends on 3) The semiconductor package structure of claim 3, wherein the substrate includes a lateral side surface and a second surface opposite to the first surface, wherein the semiconductor package structure further comprises a second encapsulant connected to the second surface of the substrate, and wherein the first portion is continuously disposed on the lateral side surface of the substrate and a lateral side surface of the second encapsulant. ### Claim 5 (depends on 1) The semiconductor package structure of claim 1, further comprising a second encapsulant encapsulating the third electronic component and in contact with the second surface of the substrate. ### Claim 6 (depends on 5) The semiconductor package structure of claim 5, wherein the substrate includes a lateral side surface extending between the first surface and the second surface, and wherein the patterned conductive layer is continuously disposed on the lateral side surface of the first encapsulant, the lateral side surface of the substrate, and a lateral side surface of the second encapsulant. ### Claim 7 A semiconductor package structure, comprising: a circuit structure; an encapsulant connected to the circuit structure and including an upper surface and a first lateral side surface; a plurality of first patterned conductive layers disposed on the upper surface and the first lateral side surface of the encapsulant and separated from each other; and a first electronic component disposed over the encapsulant and electrically connected to the circuit structure through the plurality of first patterned conductive layers, wherein a portion of the first lateral side surface of the encapsulant is exposed by the plurality of first patterned conductive layers. ### Claim 8 (depends on 7) The semiconductor package structure of claim 7, further comprising: a plurality of second patterned conductive layers disposed on the upper surface and the first lateral side surface of the encapsulant, and a second electronic component disposed over the encapsulant and electrically connected to the circuit structure through the plurality of second patterned conductive layers. ### Claim 9 (depends on 8) The semiconductor package structure of claim 8, wherein a width of the plurality of first patterned conductive layers and a width of the plurality of second patterned conductive layers are different from a top view. ### Claim 10 (depends on 8) The semiconductor package structure of claim 8, wherein the plurality of second patterned conductive layers are not electrically connected to the plurality of first patterned conductive layers. ### Claim 11 (depends on 7) The semiconductor package structure of claim 7, wherein the encapsulant comprises a second lateral side surface opposite to the first lateral side surface, and wherein the semiconductor package structure comprises: a plurality of third patterned conductive layers disposed on the upper surface and the second lateral side surface of the encapsulant, and a third electronic component disposed over the encapsulant and electrically connected to the circuit structure through the plurality of third patterned conductive layers. ### Claim 12 (depends on 11) The semiconductor package structure of claim 11, wherein a pitch of the plurality of first patterned conductive layers and a pitch of the plurality of third patterned conductive layers are different from a top view. ### Claim 13 (depends on 11) The semiconductor package structure of claim 11, wherein a portion of the second lateral side surface of the encapsulant is exposed by the plurality of third patterned conductive layers. ### Claim 14 (depends on 7) The semiconductor package structure of claim 7, wherein one of the plurality of first patterned conductive layers includes a first portion and a second portion disposed on the upper surface of the encapsulant, wherein a first extension direction of the first portion is substantially perpendicular to a second extension direction of the second portion from a top view. ### Claim 15 (depends on 14) The semiconductor package structure of claim 14, wherein a width of the first portion and a width of the second portion are different. ### Claim 16 A semiconductor package structure, comprising: a circuit structure; an encapsulant connected to the circuit structure and including an upper surface and a first lateral side surface; a plurality of first patterned conductive layers disposed on the upper surface and the first lateral side surface of the encapsulant and separated from each other; and a first electronic component disposed over the encapsulant and electrically connected to the circuit structure through the plurality of first patterned conductive layers, wherein the plurality of first patterned conductive layers include at least two different widths from a top view. ### Claim 17 A semiconductor package structure, comprising: a substrate including a first surface; a first encapsulant covering the first surface of the substrate and including an upper surface and a lateral side surface; a patterned conductive layer extending on the upper surface and the lateral side surface of the first encapsulant; and a first electronic component disposed on the patterned conductive layer; and a second electronic component encapsulated by the first encapsulant and electrically connected to the first electronic component through the substrate and the patterned conductive layer, wherein the patterned conductive layer includes a second portion disposed on the upper surface of the first encapsulant, and wherein the second portion includes a first lateral side surface and a first recess recessed from the first lateral side surface from a cross-sectional view. ### Claim 18 (depends on 17) The semiconductor package structure of claim 17, wherein the second portion includes a second lateral side surface opposite to the first lateral side surface and a second recess recessed from the second lateral side surface from the cross-sectional view.