# US 11,908,777 B2 · Semiconductor package with plurality of leads and sealing resin > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,777 B2 - Document ID: US11908777B2 - Status: Granted - Kind: B2 - Application number: 17/826,975 - Filed: 2022-05-27 - Published: 2022-09-15 - Granted: 2024-02-20 - Earliest claimed: 2016-02-15 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Mamoru Yamagami - Web page: https://patentgrep.com/patent/US11908777B2 ## CPC - H10W 70/417: {Bonding materials between chips and die pads} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps} - H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 70/466: {Tape carriers or flat leads} - H10W 72/071: {Connecting or disconnecting} - H10W 74/016: {using moulds} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/421: {Shapes or dispositions} - H10W 72/0198: {batch processes} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/811: {Multiple chips on leadframes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads. ## Claims ### Claim 1 A semiconductor device comprising: leads each including a lead body portion having an upper surface as a chip mount portion and a lower surface, a lead connecting portion having a lower surface for external connection, the lower surface projects downward from the lower surface of the lead body portion, and an inner corner portion defined between the lead connecting portion and the lower surface of the lead body portion and having a curved shape; a first sealing resin that is formed below the lead body portions and in contact with both of the inner corner portion and the lead connecting portion; a semiconductor chip that includes electrode pads electrically connected to corresponding upper surfaces of the lead body portions and that has a facing surface facing to the upper surfaces of the lead body portions and the upper surface of the first sealing resin; and a second sealing resin that enters into a region between the upper surface of the first sealing resin and the semiconductor chip, and that seals the upper surfaces of the leads, the upper surface of the first sealing resin and the semiconductor chip on the lead body portions, and that forms a boundary surface with the upper surfaces of the lead body portions and the upper surface of the first sealing resin, and wherein the lower surface of each lead connecting portion of the leads is exposed from the lower surface of the first sealing resin. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second sealing resin includes a same resin material as the resin material of the first sealing resin. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first sealing resin has a side surface, and the second sealing resin has a side surface formed flush with the side surface of the first sealing resin. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the side surface of the first sealing resin is a grinding surface, and the side surface of the second sealing resin is a grinding surface. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the electrode pads to be externally connected of the semiconductor chip are connected to the upper surfaces of the lead body portions. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the electrode pads to be externally connected of the semiconductor chip face the first sealing resin with the lead body portions located between the electrode pads and the first sealing resin. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the electrode pads to be externally connected of the semiconductor chip are connected only to the upper surfaces of the lead body portions. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein: the lead connecting portions each includes a base portion projecting downward from the lower surface of the lead body portion, and a plated layer formed on the base portion and forming a lower surface of the lead connecting portion, the inner corner portions of the leads each connects the lead body portion and the base portion of the lead connecting portions, and the first sealing resin covers the base portions and the plated layers inside the space defined by the leads. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the lead connecting portions each has a side surface formed by the base portion and the plated layer. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the plated layer exposes a portion forming the side surface of the lead connecting portion in the base portion. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein the first sealing resin has side surfaces exposing the side surfaces of the lead connecting portions. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the side surfaces of the first sealing resin are formed flush with the side surfaces of the lead connecting portions. ### Claim 13 (depends on 8) The semiconductor device according to claim 8, wherein the first sealing resin has a lower surface that exposes the plated layers of the lead connecting portions. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the lower surface of the first sealing resin is formed flush with the plated layers of the lead connecting portions. ### Claim 15 (depends on 8) The semiconductor device according to claim 8, wherein: the plated layers each has a laminated structure including an Ni layer, a Pd layer, and an Au layer laminated in this order on the base portion, and the first sealing resin has a lower surface exposing the Au layers of the plated layers. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the lower surface of the first sealing resin is formed flush with the Au layers of the plated layers. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the leads each includes a lead notched portion notching a corner portion at an opposite side to the space in a lower surface of the lead connecting portion in a step shape. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the lead notched portions each has an outer corner portion having a curvature lower than a curvature of the inner corner portion of the leads. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein the outer corner portions of the lead notched portions are angularly formed. ### Claim 20 (depends on 17) The semiconductor device according to claim 17, further comprising notched plated layers covering wall surfaces of the lead notched portions. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the notched plated layers each covers the lower surface of the lead connecting portion and expose a lateral wall of the lead connecting portion. ### Claim 22 (depends on 21) The semiconductor device according to claim 21, wherein the first sealing resin has side surfaces exposing the side surfaces of the lead connecting portions. ### Claim 23 (depends on 22) The semiconductor device according to claim 22, wherein the side surfaces of the first sealing resin are formed flush with the side surfaces of the lead connecting portions. ### Claim 24 (depends on 17) The semiconductor device according to claim 17, wherein the first sealing resin includes a resin notched portion notching a corner portion of a lower surface of the first sealing resin in a step shape and communicating with the lead notched portions of the leads. ### Claim 25 (depends on 1) The semiconductor device according to claim 1, wherein, the leads each includes a thin portion formed by the lead body portion and a thick portion formed by the lead body portion and the lead connecting portion, the first sealing resin supports the thin portions from directly below the thin portions in the space defined by the leads, and the semiconductor chip is arranged only on the thin portions of the leads. ### Claim 26 (depends on 25) The semiconductor device according to claim 25, wherein, the semiconductor chip does not overlap with the thick portions of the leads as viewed in plan. ### Claim 27 (depends on 1) The semiconductor device according to claim 1, further comprising: a chip part that includes a chip body having a functional element and a plurality of external terminals formed on the chip body and connected to corresponding upper surfaces of the lead body portions of the leads. ### Claim 28 (depends on 27) The semiconductor device according to claim 27, wherein, the leads include first leads and second leads, the electrode pads of the semiconductor chip are connected to upper surfaces of the lead body portions of the first leads, and the external terminals of the chip part are connected to upper surfaces of the lead body portions of the second leads. ### Claim 29 (depends on 27) The semiconductor device according to claim 27, wherein, only the first sealing resin is placed in an area directly below the chip part in the space defined by the leads, and the lower surface of the first sealing resin is overlapped with an entire region of a surface of the chip part as viewed in plan. ### Claim 30 (depends on 1) The semiconductor device according to claim 1, wherein: the lead connecting portion includes a base portion projecting downward from the lower surface of the lead body portion, the inner corner portion of the lead connects the lead body portion and the base portion of the lead connecting portion, and the first sealing resin is in contact with a side surface of the base portion. ### Claim 31 (depends on 30) The semiconductor device according to claim 30, wherein the first sealing resin surrounds the base portion. ### Claim 32 (depends on 31) The semiconductor device according to claim 31, a plated layer is formed on a lower surface of the base portion. ### Claim 33 (depends on 32) The semiconductor device according to claim 32, a plated layer is formed on the side surface of the base portion.