# US 11,908,776 B2 · Semiconductor device with metal die attach to substrate with multi-size cavity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,776 B2 - Document ID: US11908776B2 - Status: Granted - Kind: B2 - Application number: 17/142,598 - Filed: 2021-01-06 - Published: 2021-04-29 - Granted: 2024-02-20 - Earliest claimed: 2019-03-25 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Benjamin Stassen Cook; Nazila Dadvand; Sreenivasan Koduri - Web page: https://patentgrep.com/patent/US11908776B2 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/417: {Bonding materials between chips and die pads} - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/778: {in encapsulations} - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 70/461: {specially adapted for cooling} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/68: Shapes or dispositions thereof - H10W 70/635: {Through-vias} - H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL} - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/874: {On different surfaces} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate. ## Claims ### Claim 1 A method of semiconductor die attachment, comprising: providing at least one metal substrate including a top cavity portion that is sized with area dimensions to receive a semiconductor die having a top side with bond pads thereon and a back side with a metal (BSM) layer thereon; forming a through-hole aperture including a multi-size cavity by removing metal from an area portion of the top cavity portion and from a bottom cavity portion to form a first ring around the bottom cavity portion; inserting the semiconductor die top side up to place the BSM layer on the first ring, and immersing at least the BSM layer of the semiconductor die and a bottom side of the metal substrate into a plating container that provides an electroplating bath including an electroplating solution to plate a metal die attach layer that directly contacts at least a portion of the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate. ### Claim 2 (depends on 1) The method of claim 1, further comprising before the plating: sealing with a dielectric cover the top side of the semiconductor die including along a periphery between the dielectric cover and the metal substrate to a provide a sealed die and to secure the semiconductor die in the through-hole aperture; wherein the plating comprises immersing the sealed die in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, and after the plating, removing the dielectric cover. ### Claim 3 (depends on 2) The method of claim 2, wherein the metal electroplating solution comprises a copper electroplating solution. ### Claim 4 (depends on 1) The method of claim 1, wherein the BSM layer, the metal substrate, and the metal die attach layer all comprise copper. ### Claim 5 (depends on 1) The method of claim 1, wherein the removing metal comprises a masked etch. ### Claim 6 (depends on 1) The method of claim 1, wherein the metal die attach layer is 40 to 250 μm thick. ### Claim 7 (depends on 1) The method of claim 1, wherein the metal die attach layer consists of a single layer. ### Claim 8 A method of semiconductor die attachment, comprising: providing at least one metal substrate including a top cavity portion that is sized with area dimensions to receive a semiconductor die having a top side with bond pads thereon and a back side with a metal (BSM) layer thereon; forming a through-hole aperture including a multi-size cavity by removing metal from an area portion of the top cavity portion and from a bottom cavity portion to form a first ring around the bottom cavity portion; inserting the semiconductor die top side up to place the BSM layer on the first ring, and plating a metal die attach layer that directly contacts at least a portion of the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate. ### Claim 9 (depends on 8) The method of claim 8, further comprising before the plating: sealing with a dielectric cover the top side of the semiconductor die including along a periphery between the dielectric cover and the metal substrate to a provide a sealed die and to secure the semiconductor die in the through-hole aperture; wherein the plating comprises immersing the sealed die in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, and after the plating, removing the dielectric cover. ### Claim 10 (depends on 9) The method of claim 9, wherein the metal electroplating solution comprises a copper electroplating solution. ### Claim 11 (depends on 8) The method of claim 8, wherein the BSM layer, the metal substrate, and the metal die attach layer all comprise copper. ### Claim 12 (depends on 8) The method of claim 8, wherein the metal die attach layer is 40 to 250 μm thick. ### Claim 13 (depends on 8) The method of claim 8, wherein the metal die attach layer consists of a single layer. ### Claim 14 A method of semiconductor die attachment, comprising: providing at least one metal substrate including a multi-size cavity including a top cavity portion that is sized with area dimensions to receive a semiconductor die having a top side with bond pads thereon and a back side with a metal (BSM) layer thereon and a bottom cavity portion that defines a first ring around the bottom cavity portion; placing the BSM layer of the semiconductor die on the first ring, and plating a metal die attach layer that directly contacts at least a portion of the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate. ### Claim 15 (depends on 14) The method of claim 14, further including a thru-hole aperture within the bottom cavity portion. ### Claim 16 (depends on 15) The method of claim 15, further comprising before the plating: sealing with a dielectric cover the top side of the semiconductor die including along a periphery between the dielectric cover and the metal substrate to a provide a sealed die and to secure the semiconductor die in the through-hole aperture; wherein the plating comprises immersing the sealed die in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, and after the plating, removing the dielectric cover. ### Claim 17 (depends on 14) The method of claim 14, wherein the metal electroplating solution comprises a copper electroplating solution. ### Claim 18 (depends on 14) The method of claim 14, wherein the BSM layer, the metal substrate, and the metal die attach layer all comprise copper. ### Claim 19 (depends on 14) The method of claim 14, wherein the metal die attach layer is 40 to 250 μm thick. ### Claim 20 (depends on 14) The method of claim 14, wherein the metal die attach layer consists of a single layer.