# US 11,908,775 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,775 B2 - Document ID: US11908775B2 - Status: Granted - Kind: B2 - Application number: 17/645,472 - Filed: 2021-12-22 - Published: 2022-11-10 - Granted: 2024-02-20 - Earliest claimed: 2021-05-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jaewon Hwang; Kwangjin Moon; Hojin Lee; Hyungjun Jeon - Web page: https://patentgrep.com/patent/US11908775B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/075: {of multilayered thin functional dielectric layers} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/481: {on the rear surfaces of the wafers or substrates} - H10W 72/30: Die-attach connectors - H10W 72/50: Bond wires - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/29: Bond pads specially adapted therefor - H10W 72/90: Bond pads, in general - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and comprising a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern, wherein an upper surface of the contact wiring pattern is higher than a lower surface of the etch stop structure, and is not higher than an upper surface of the etch stop structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the etch stop structure comprises: a first etch stop layer disposed on a lower portion of the first insulating layer and configured to surround a part of a side surface of the through electrode structure; a second etch stop layer disposed on a lower portion of the first etch stop layer, configured to surround a part of the side surface of the through electrode structure, and configured to contact the contact wiring pattern; and a third etch stop layer disposed between the second etch stop layer and the second insulating layer and configured to surround a part of a side surface of the contact wiring pattern. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein a lower surface of the second etch stop layer is coplanar with the upper surface of the contact wiring pattern. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein a material of the first etch stop layer is different from a material of the second etch stop layer, and the material of the first etch stop layer is the same as a material of the third etch stop layer. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein an etch rate of the material of the first etch stop layer in a dry etching process is lower than an etch rate of the material of the second etch stop layer in the dry etching process. ### Claim 6 (depends on 4) The semiconductor device of claim 4, wherein the material of the first etch stop layer comprises at least one of nickel (Ni), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), aluminum (Al), or ruthenium (Ru), and the material of the second etch stop layer comprises at least one of silicon (Si), carbon (C), oxygen (O), nitrogen (N), or hydrogen (H). ### Claim 7 (depends on 2) The semiconductor device of claim 2, wherein each of the first etch stop layer, the second etch stop layer, and the third etch stop layer has a thickness of about 1 nanometer to about 10 nanometers. ### Claim 8 (depends on 2) The semiconductor device of claim 2, further comprising: a separation layer interposed between the through electrode structure and the semiconductor substrate, between the through electrode structure and the first insulating layer, and between the through electrode structure and the first etch stop layer. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the through electrode structure comprises: a barrier pattern disposed along a surface of the separation layer and configured to contact the contact wiring pattern; a seed pattern disposed along a surface of the barrier pattern; and a conductive via disposed on the seed pattern and filled in a via hole defined by the barrier pattern and the seed pattern, wherein uppermost surfaces of the barrier pattern, the seed pattern, and the conductive via are coplanar with each other. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein a width of the through electrode structure is about 30 nanometers to about 200 nanometers. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the through electrode structure comprises: a first through electrode portion configured to overlap the contact wiring pattern in the vertical direction; and a second through electrode portion disposed outside from a side surface of the contact wiring pattern.