# US 11,908,774 B2 · Semiconductor package including composite molding structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,774 B2 - Document ID: US11908774B2 - Status: Granted - Kind: B2 - Application number: 17/850,504 - Filed: 2022-06-27 - Published: 2022-10-13 - Granted: 2024-02-20 - Earliest claimed: 2020-02-27 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Heeseok Lee; Yunhyeok Im - Web page: https://patentgrep.com/patent/US11908774B2 ## CPC - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/611: {for connecting multiple chips together} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 70/68: Shapes or dispositions thereof - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 40/60: Securing means for detachable heating or cooling arrangements, e.g. clamps - H10W 40/778: {in encapsulations} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/01: Manufacture or treatment - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 74/473: {containing a filler} - H10W 90/20: Configurations of stacked chips - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material. ## Claims ### Claim 1 A semiconductor package, comprising: a lower semiconductor chip mounted on a top surface of a lower package substrate; an interposer disposed above the lower package substrate and including an opening; a first molding member including a first material, filling the opening; and a second molding member including a second material different from the first material, covering a top surface of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends to protrude from the top surface of the interposer, wherein the protrusion covers a portion of the top surface of the interposer, and wherein the protrusion has a first width in a first direction greater than a second width in the first direction of the first molding member below a bottom surface of the interposer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the opening has a third width along the first direction, the lower semiconductor chip has a fourth width in the first direction, and the third width is smaller than the fourth width. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first molding member is vertically spaced apart from the lower semiconductor chip with the second molding member interposed therebetween. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the first molding member is spaced apart from the lower package substrate. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein when viewed in plan, the first molding member partially overlaps the top surface of the lower semiconductor chip. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the second molding member extends between the lower semiconductor chip and the first molding member. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first material has a thermal conductivity greater than a thermal conductivity of the second material. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the first material includes at least one of copper paste, silver paste and an epoxy molding compound containing a metal filler, and the second material is non-conductive. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the second material has a polymer density greater than a polymer density of the first material. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the first molding member and the second molding member contact each other, and have therebetween a boundary positioned on the top surface of the lower semiconductor chip.