# US 11,908,764 B2 · Semiconductor package including a circuit substrate having a cavity and a floor plate embedded in a dielectric material and a semiconductor die disposed in the cavity

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- Number: US 11,908,764 B2
- Document ID: US11908764B2
- Status: Granted
- Kind: B2
- Application number: 17/462,000
- Filed: 2021-08-31
- Published: 2023-03-02
- Granted: 2024-02-20
- Earliest claimed: 2021-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Liang Lin; Po-Yao Chuang; Te-Chi Wong; Shuo-Mao Chen; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US11908764B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

## Claims

### Claim 1

A semiconductor package comprising:
a circuit substrate having a first surface, a second surface opposite to the first surface and a cavity concave from the first surface, wherein the circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity, wherein the metal floor plate includes a plurality of metal plates, a location of the metal floor plate corresponds to a location of the cavity, both top and bottom surfaces of the metal floor plate are fully covered by the dielectric material, and the metal floor plate is electrically floating and isolated by the dielectric material;
a semiconductor die, disposed in the cavity and electrically connected with the circuit substrate; and
a filling material, disposed between the semiconductor die and the circuit substrate, wherein the filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising a redistribution layer disposed on and connected to an active surface of the semiconductor die and connected to the first surface of the circuit substrate.

### Claim 3 (depends on 2)

The semiconductor package as claimed in claim 2, wherein the semiconductor die is electrically connected with the circuit substrate via the redistribution layer.

### Claim 4 (depends on 2)

The semiconductor package as claimed in claim 2, further comprising a molded structure disposed on the redistribution layer, wherein the molded structure includes another semiconductor die electrically connected with the redistribution layer and the semiconductor die and electrically connected with the circuit substrate.

### Claim 5 (depends on 4)

The semiconductor package as claimed in claim 4, wherein the redistribution layer includes vertically stacking metallization patterns, and the semiconductor die is electrically connected with the another semiconductor die through the vertically stacking metallization patterns.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the semiconductor die includes through semiconductor vias (TSVs) penetrating through the semiconductor die and the semiconductor die is electrically connected with the circuit substrate via the TSVs.

### Claim 7 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a bottom of the cavity is spaced apart from the metal floor plate with a distance with the dielectric material sandwiched therebetween.

### Claim 8 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a vertical projection of the cavity falls within a span of the metal floor plate.

### Claim 9 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a vertical projection of the cavity overlaps the metal floor plate.

### Claim 10

A package comprising:
a redistribution layer having a first surface and a second surface opposite to the first surface;
a molded structure disposed on the first surface of the redistribution layer, wherein the molded structure includes a first die and a second die laterally surrounded by a molding compound, and the first and second dies are electrically connected with the redistribution layer;
a circuit substrate connected with the second surface of the redistribution layer, wherein the circuit substrate includes a dielectric material, a cavity concave into the dielectric material and having metal-free dielectric surfaces, and a floor plate embedded in the dielectric material with both top and bottom surfaces of the floor plate being fully covered by the dielectric material and located below the cavity, wherein the floor plate includes a single metallic plate with a mesh pattern, and a vertical projection of the cavity overlaps the single metallic plate;
a third die, disposed on the second surface of the redistribution layer, located in the cavity and electrically connected with the redistribution layer; and
an underfill, disposed between the third die and the cavity and between the circuit substrate and the redistribution layer.

### Claim 11 (depends on 10)

The package as claimed in claim 10, wherein the dielectric material sandwiched between the floor plate and a bottom of the cavity has a thickness ranging from about 1 micron to about 100 microns.

### Claim 12 (depends on 10)

The package as claimed in claim 10, wherein a vertical projection of the cavity falls within a span of the floor plate, and the span of the floor plate is larger than a span of the cavity.

### Claim 13 (depends on 10)

The package as claimed in claim 10, wherein a back surface of the third die is distanced from a bottom of the cavity with a distance ranging from about 1 micron to about 100 microns.

### Claim 14 (depends on 10)

The package as claimed in claim 10, wherein the third die is encapsulated by the underfill and the third die is electrically connected with the circuit substrate via the redistribution layer.

### Claim 15 (depends on 10)

The package as claimed in claim 10, wherein the third die includes through semiconductor vias (TSVs) penetrating through the third die and the third die is electrically connected with the circuit substrate via the TSVs.

### Claim 16

A package comprising:
a redistribution layer having a first surface and a second surface opposite to the first surface;
a molded structure disposed on the first surface of the redistribution layer, wherein the molded structure includes a first die and a second die laterally surrounded by a molding compound, and the first and second dies are electrically connected with the redistribution layer;
a circuit substrate connected with the second surface of the redistribution layer, wherein the circuit substrate includes a dielectric material, a cavity concave into the dielectric material and having metal-free dielectric surfaces, and a floor plate embedded in the dielectric material with both top and bottom surfaces of the floor plate being fully covered by the dielectric material and located below the cavity, wherein the floor plate includes multiple parallel arranged metallic plates, and a vertical projection of the cavity overlaps the multiple parallel arranged metallic plates;
a third die, disposed on the second surface of the redistribution layer, located in the cavity and electrically connected with the redistribution layer; and
an underfill, disposed between the third die and the cavity and between the circuit substrate and the redistribution layer.

### Claim 17 (depends on 16)

The package as claimed in claim 16, wherein the dielectric material sandwiched between the floor plate and a bottom of the cavity has a thickness ranging from about 1 micron to about 100 microns.

### Claim 18 (depends on 16)

The package as claimed in claim 16, wherein a back surface of the third die is distanced from a bottom of the cavity with a distance ranging from about 1 micron to about 100 microns.

### Claim 19 (depends on 16)

The package as claimed in claim 16, wherein the third die is encapsulated by the underfill and the third die is electrically connected with the circuit substrate via the redistribution layer.

### Claim 20 (depends on 16)

The package as claimed in claim 16, wherein the third die includes through semiconductor vias (TSVs) penetrating through the third die and the third die is electrically connected with the circuit substrate via the TSVs.