# US 11,908,759 B2 · Semiconductor device

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- Number: US 11,908,759 B2
- Document ID: US11908759B2
- Status: Granted
- Kind: B2
- Application number: 17/190,584
- Filed: 2021-03-03
- Published: 2021-06-24
- Granted: 2024-02-20
- Earliest claimed: 2016-10-06
- Assignees: Mediatek Inc.
- Applicants: MediaTek Inc.
- Inventors: Nan-Cheng Chen; Che-Ya Chou; Hsing-Chih Liu; Che-Hung Kuo
- Web page: https://patentgrep.com/patent/US11908759B2

## CPC

- H10W 74/10: characterised by their shape or disposition
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 70/695: Organic materials
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/9413: {on encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate; and
a body structure disposed above the substrate and comprising:
a semiconductor die having an active surface;
a molding compound encapsulating the semiconductor die and having a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface;
a conductive component formed within the through hole;
a lower redistribution layer (RDL) formed on the lower surface of the molding compound, the conductive component being exposed from the lower surface; and
a first electronic component disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component,
wherein the molding compound is not present between the active surface of the semiconductor die and the lower RDL.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the body structure further comprises:
an upper RDL formed on the upper surface of the molding compound and electrically connected to the conductive component;
wherein the first electronic component partly overlaps the semiconductor die in a stack direction of the first electronic component and the semiconductor die.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, further comprising a second electronic component that partly overlaps the semiconductor die in a stack direction of the second electronic component and the semiconductor die.

### Claim 4 (depends on 2)

The semiconductor device as claimed in claim 2, further comprising a second electronic component, wherein the second electronic component does not overlap the semiconductor die.

### Claim 5 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the upper RDL comprises:
an upper passivation layer having an upper surface; and
a conductive pad formed projecting from the upper surface of the upper passivation layer;
wherein the first electronic component has a first conductive contact, and the first electronic component is disposed on the conductive pad by the first conductive contact.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, further comprising:
an underfill between the first electronic component and the body structure, the underfill encapsulating the first conductive contact.

### Claim 7 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the upper RDL further comprises:
an upper conductive layer formed beneath the upper passivation layer; and
an upper dielectric layer formed between the upper conductive layer and the upper surface of the molding compound.

### Claim 8 (depends on 7)

The semiconductor device as claimed in claim 7, wherein the upper dielectric layer has at least one upper opening, wherein the upper conductive layer is electrically connected to the conductive component through the at least one upper opening.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first electronic component partly overlaps the semiconductor die in a stack direction of the first electronic component and the semiconductor die.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the lower RDL extends beyond a lateral surface of the semiconductor die to form a fan-out structure.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the lower RDL comprises a lower conductive layer that extends beyond the lateral surface of the semiconductor die and is electrically connected to the conductive component.

### Claim 12 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the lower RDL further comprises:
a lower dielectric layer formed between the lower surface of the molding compound and the lower conductive layer, the lower dielectric layer having a first lower opening that exposes the conductive component;
wherein the lower conductive layer is electrically connected to the conductive component through the first lower opening.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, further comprising:
a lower passivation layer formed below the lower conductive layer and having a second lower opening; and
a second conductive contact formed within the second lower opening.

### Claim 14 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an underfill between the body structure and the substrate, wherein the first underfill encapsulates the lower RDL.

### Claim 15 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the substrate comprises:
a plurality of upper pads; and
a plurality of lower pads electrically connected to the plurality of upper pads through vias.

### Claim 16 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the substrate is electrically connected to the body structure through at least one of the plurality of upper pads.

### Claim 17 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first electronic component is electrically connected to the substrate through the conductive component and the lower RDL.

### Claim 18 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first electronic component is a High Bandwidth Memory (HBM).

### Claim 19 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the semiconductor die is a System on Chip.

### Claim 20 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the semiconductor die is formed by a silicon wafer.