# US 11,908,749 B2 · Method of metal gate formation and structures formed by the same

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- Number: US 11,908,749 B2
- Document ID: US11908749B2
- Status: Granted
- Kind: B2
- Application number: 18/057,741
- Filed: 2022-11-21
- Published: 2023-03-16
- Granted: 2024-02-20
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Yi-Jing Lee; Ya-Yun Cheng; Hau-Yu Lin; I-Sheng Chen; Chia-Ming Hsu; Chih-Hsin Ko; Clement Hsingjen Wann
- Web page: https://patentgrep.com/patent/US11908749B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 50/264: {by chemical means}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
providing a substrate;
providing a first gate electrode over the substrate;
forming a first pair of spacers on two sides of the first gate electrode;
removing the first gate electrode to form a first trench between the first pair of spacers;
depositing a dielectric layer in the first trench;
depositing a first layer over the dielectric layer;
removing the first layer from the first trench; and
depositing a work function layer over the dielectric layer in the first trench.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
providing a second gate electrode over the substrate;
forming a second pair of spacers on two sides of the second gate electrode; and
removing the second gate electrode to form a second trench between the second pair of spacers,
wherein the depositing of the first layer over the dielectric layer comprises depositing the first layer in the second trench.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the removing of the first layer from the first trench comprises keeping the first layer substantially intact in the second trench.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the depositing of the first layer over the dielectric layer comprises depositing the first layer on a sidewall of the dielectric layer.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising forming an adhesive layer in the first trench over the work function layer.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising depositing an interlayer dielectric layer to surround the first gate electrode prior to removing the first gate electrode.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the removing the first gate electrode comprises exposing the first pair of spacers.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
depositing a second layer over the first layer prior to depositing the work function layer; and
partially removing the second layer.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising depositing a conductive layer over the work function layer and filling the first trench.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the conductive layer comprises a top surface having a first width and a bottom surface having a second width greater than the first width.

### Claim 11 (depends on 9)

The method according to claim 9, wherein the conductive layer comprises a top surface having a first width, and a ratio between the first width and a maximal width of the conductive layer is less than about 30%.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the maximal width is measured at a first height measured from a surface of the substrate, between about 10% and about 30% of a second height of the dielectric layer measured from the surface of the substrate.

### Claim 13

A method of forming a semiconductor structure, comprising:
forming a first pair of source/drain regions and a second pair of source/drain regions in a substrate;
depositing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions and a second trench between the second pair of source/drain regions;
forming a layer stack over the interlayer dielectric layer in the first trench and the second trench, wherein the layer stack has a first number of layers in the first trench and a second number of layers, different from the first number of layers, in the second trench; and
depositing a conductive layer in the first trench and the second trench over the layer stack.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the forming of the layer stack over the interlayer dielectric layer in the first trench and the second trench comprises reducing a thickness of the layer stack from the first trench.

### Claim 15 (depends on 14)

The method according to claim 14, further comprising performing a cleaning operation on the substrate prior to reducing the thickness of the layer stack from the first trench.

### Claim 16 (depends on 14)

The method according to claim 14, further comprising depositing a gate dielectric layer in the first trench and the second trench prior to forming the layer stack, wherein the reducing of the thickness of the layer stack from the first trench comprises removing the layer stack to expose the gate dielectric layer.

### Claim 17 (depends on 14)

The method according to claim 14, wherein the reducing of the thickness of the layer stack from the first trench comprises performing a wet etching operation.

### Claim 18 (depends on 13)

The method according to claim 13, wherein the layer stack comprises at least one of titanium nitride, titanium silicon nitride and tantalum nitride.

### Claim 19

A method of forming a semiconductor structure, comprising:
forming a first dummy gate electrode and a second dummy gate electrode over a substrate;
forming first spacers on the first dummy gate electrode and second spacers on the second dummy gate electrode;
depositing an interlayer dielectric layer over the first and second dummy gate electrodes and the substrate;
etching the first and second dummy gate electrodes to form a first trench between the first spacers and a second trench between the second spacers;
depositing a layer stack in the first trench and the second trench;
depositing a work function layer over the layer stack;
etching at least a portion of the work function layer from the first trench while keeping the work function layer and the layer stack intact in the second trench; and
depositing a conductive layer to fill the first trench and the second trench.

### Claim 20 (depends on 19)

The method according to claim 19, further comprising performing an annealing operation subsequent to depositing the layer stack and prior to depositing the work function layer.