# US 11,908,748 B2 · Semiconductor devices and methods of forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,908,748 B2
- Document ID: US11908748B2
- Status: Granted
- Kind: B2
- Application number: 18/055,498
- Filed: 2022-11-15
- Published: 2023-03-16
- Granted: 2024-02-20
- Earliest claimed: 2020-02-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Feng-Ching Chu; Wei-Yang Lee; Feng-Cheng Yang; Yen-Ming Chen
- Web page: https://patentgrep.com/patent/US11908748B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/853: {comprising FinFETs}
- H10P 50/242: {of Group IV materials}
- H10P 50/287: {by chemical means}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/73: {using masks for insulating materials}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a first region and a second region of opposite conductivity types;
an isolation feature over the substrate;
a first fin protruding from the substrate and through the isolation feature in the first region;
a first epitaxial feature over the first fin;
a second fin protruding from the substrate and through the isolation feature in the second region; and
a second epitaxial feature over the second fin,
wherein a portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the isolation feature includes a first sidewall facing the first fin and a second sidewall facing the second fin, and wherein at least one of the first and second sidewalls is substantially perpendicular to the top surface of the isolation feature.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein each of the first and second sidewalls is substantially perpendicular to the top surface of the isolation feature.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein another one of the first and second sidewalls is tilted with respect to the one of the first and second sidewalls.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the isolation feature is fully located in one of the first and second regions.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the isolation feature laterally expands across a boundary between the first and second regions.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the isolation feature protrudes from the top surface of the isolation feature for a first vertical distance, the top surface of the isolation feature is spaced from the substrate for a second vertical distance, and a ratio between the first vertical distance and the second vertical distance ranges from about 2:5 to about 3:4.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the isolation feature is above a bottom surface of the first epitaxial feature.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the portion of the isolation feature is above a bottom surface of the second epitaxial feature.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate;
an isolation feature over the semiconductor substrate;
a fin protruding from the semiconductor substrate and through the isolation feature;
a gate structure engaging the fin;
a sidewall spacer disposed on sidewalls of the gate structure; and
an epitaxial feature over the fin,
wherein the isolation feature includes a first portion having a first thickness and a second portion having a second thickness that is larger than the first thickness, the first portion is located between the fin and the second portion, and a top surface of the first portion extends continuously to a sidewall of the second portion.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the sidewall of the second portion is substantially perpendicular to the top surface of the first portion.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the sidewall spacer extends to sidewalls of the epitaxial feature.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the isolation feature includes a third portion directly under the sidewall spacer and in contact with the sidewalls of the epitaxial feature, and wherein the third portion has a third thickness that is larger than the first thickness.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the third thickness is substantially equal to the second thickness.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein a topmost portion of the second portion of the isolation feature is above a top surface of the fin.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the semiconductor substrate includes a first region of a first conductivity type and a second region of a second conductivity type that is opposite to the first conductivity type, the fin is located in the first region, and the second portion of the isolation feature laterally expands across the first and second regions.

### Claim 17

A method of forming a semiconductor device, comprising:
providing a structure that includes a substrate, a fin protruding from the substrate, an isolation feature surrounding the fin, and a gate structure engaging the fin;
depositing a resist layer covering the fin, the isolation feature, and the gate structure;
performing a first etching process to recess the resist layer below a top surface of the gate structure;
performing a second etching process to further recess the resist layer;
performing a third etching process to remove the resist layer, wherein the first, second, and third etching processes have different etching rates;
recessing the fin; and
forming an epitaxial feature above the fin.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second etching process has a highest etching rate among the first, second, and third etching processes.

### Claim 19 (depends on 17)

The method of claim 17, wherein after the first etching process, a top surface of the fin remains covering by the resist layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein after the second etching process, the top surface of the fin remains covering by the resist layer.