# US 11,908,746 B2 · Semiconductor devices and methods of manufacturing thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,746 B2 - Document ID: US11908746B2 - Status: Granted - Kind: B2 - Application number: 17/460,213 - Filed: 2021-08-28 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2021-08-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Kuei-Yu Kao; Chao-Cheng Chen; Chih-Han Lin; Chen-Ping Chen; Ming-Ching Chang; Shih-Yao Lin; Chih-Chung Chiu - Web page: https://patentgrep.com/patent/US11908746B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 84/0147: {Manufacturing their gate sidewall spacers} - H10D 84/0158: {the components including FinFETs} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees. ## Claims ### Claim 1 A semiconductor device, comprising: a plurality of semiconductor layers vertically separated from one another; a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers; an etch stop layer; and a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface; wherein a portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees; and wherein the etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the gate structure has a lower side portion extending between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the etch stop layer has a sidewall vertically aligned with the sidewall of the upper portion of the gate structure. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the gate spacer comprises a plurality of dielectric layers. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein at least one of the plurality of dielectric layers has a tilted portion that forms the bottom surface of the gate spacer. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the tilted portion is in contact with the top surface of the topmost semiconductor layer. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the tilted portion extends away from the sidewall of the upper portion of the gate structure. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising a source/drain structure coupled to the plurality of semiconductor layers, wherein source/drain structure is electrically isolated from the gate structure by the gate spacer. ### Claim 9 A semiconductor device, comprising: a fin structure disposed over a substrate, wherein the fin structure includes a plurality of semiconductor layers; a gate structure that comprises a lower portion and an upper portion, wherein the lower portion straddles the fin structure; a gate spacer that extends along a sidewall of the upper portion of the gate structure and comprises a vertical portion and tilted portion, wherein the vertical portion is in contact with the sidewall and the tilted portion overlays at least a first portion of a top surface of a topmost one of the plurality of semiconductor layers; and an etch stop layer extending between the tilted portion and a second portion of the top surface of the topmost semiconductor layer that is not overlaid by the tilted portion. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the plurality of semiconductor layers are vertically separated from one another, and the gate structure wraps around each of the plurality of semiconductor layers. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein the gate structure has a lower side portion extending between the tilted portion and a second portion of the top surface of the topmost semiconductor layer that is not overlaid by the tilted portion. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein the etch stop layer has a sidewall vertically aligned with the sidewall of the upper portion of the gate structure. ### Claim 13 (depends on 9) The semiconductor device of claim 9, wherein the gate spacer comprises a plurality of dielectric layers. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein at least one of the plurality of dielectric layers has the tilted portion to form a bottom surface of the gate spacer. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein a portion of the bottom surface of the gate spacer and a second portion of the top surface of the topmost semiconductor layer that is not overlaid by the tilted portion form an angle less than 90 degrees. ### Claim 16 A semiconductor device, comprising: a plurality of semiconductor layers vertically separated from one another; a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers; a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface; wherein a portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees; wherein the gate spacer comprises a plurality of dielectric layers; wherein at least one of the plurality of dielectric layers has a tilted portion that forms the bottom surface of the gate spacer; and wherein the tilted portion extends away from the sidewall of the upper portion of the gate structure. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the gate structure has a lower side portion extending between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the tilted portion is in contact with the top surface of the topmost semiconductor layer. ### Claim 19 (depends on 16) The semiconductor device of claim 16, further comprising a source/drain structure coupled to the plurality of semiconductor layers, wherein source/drain structure is electrically isolated from the gate structure by the gate spacer. ### Claim 20 (depends on 16) The semiconductor device of claim 16, wherein the plurality of semiconductor layers are vertically separated from one another, and the gate structure wraps around each of the plurality of semiconductor layers.