# US 11,908,745 B2 · Semiconductor device with non-conformal gate dieletric layers

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- Number: US 11,908,745 B2
- Document ID: US11908745B2
- Status: Granted
- Kind: B2
- Application number: 18/182,959
- Filed: 2023-03-13
- Published: 2023-07-06
- Granted: 2024-02-20
- Earliest claimed: 2021-04-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yung-Hsiang Chan; Wen-Hung Huang; Shan-Mei Liao; Jian-Hao Chen; Kuo-Feng Yu; Kuei-Lun Lin
- Web page: https://patentgrep.com/patent/US11908745B2

## CPC

- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

## Claims

### Claim 1

A semiconductor device, comprising:
a first semiconductor layer below a second semiconductor layer;
first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and
a gate electrode surrounding both the first and the second gate dielectric layers, wherein the first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer, the second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer, wherein the first top section has a first thickness, the second top section has a second thickness, and the second thickness is greater than the first thickness.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first bottom section has a third thickness smaller than the first thickness.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a ratio of the first thickness to the third thickness is about 1:0.8 to about 1:0.99.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the second bottom section has a fourth thickness smaller than the second thickness.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a ratio of the second thickness to the fourth thickness is about 1:0.8 to about 1:0.99.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a first interfacial layer interposing between the first gate dielectric layer and the first semiconductor layer, wherein the first interfacial layer has about same thickness above and below the first semiconductor layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second thickness is greater than the first thickness by about 0.2 Å to about 0.8 Å.

### Claim 8

A semiconductor device, comprising:
a first semiconductor layer over a base semiconductor structure;
a second semiconductor layer over the first semiconductor layer;
a third semiconductor layer over the second semiconductor layer;
first, second, and third interfacial layers surrounding the first, the second, and the third semiconductor layers respectively;
first, second, and third gate dielectric layers surrounding the first, the second, and the third interfacial layers, respectively; and
a common gate electrode surrounding the first, the second, and the third gate dielectric layers, wherein each of the first, the second, and the third gate dielectric layers has asymmetric thicknesses below and above the respective first, second, and third interfacial layers.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first gate dielectric layer is thicker above the first interfacial layer than below the first interfacial layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second gate dielectric layer is thicker above the second interfacial layer than below the second interfacial layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the third gate dielectric layer is thicker above the third interfacial layer than below the third interfacial layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the first gate dielectric layer has a first average thickness above the first interfacial layer, the second gate dielectric layer has a second average thickness above the second interfacial layer, and the first average thickness is smaller than the second average thickness.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the third gate dielectric layer has a third average thickness above the third interfacial layer, and the third average thickness is greater than the second average thickness.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the first gate dielectric layer has a first average thickness below the first interfacial layer, the second gate dielectric layer has a second average thickness below the second interfacial layer, and the first average thickness is smaller than the second average thickness.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the third gate dielectric layer has a third average thickness below the third interfacial layer, and the third average thickness is greater than the second average thickness.

### Claim 16

A method, comprising:
receiving a structure in a processing chamber, wherein the structure includes multiple semiconductor layers suspended over a semiconductor substrate;
forming an interfacial layer surrounding each of the semiconductor layers;
forming a gate dielectric layer over the interfacial layer and surrounding each of the semiconductor layers; and
forming a gate electrode over the gate dielectric layer and surrounding each of the semiconductor layers,
wherein the forming of the gate dielectric layer includes:
introducing a first precursor into the processing chamber for a first duration,
performing a first purging process for a second duration,
introducing a second precursor into the processing chamber for a third duration,
performing a second purging process for a fourth duration, and
repeating the introducing the first precursor, performing the first purging process, introducing the second precursor, and performing the second purging process to form the gate dielectric layer having asymmetric thicknesses around each of the semiconductor layers.

### Claim 17 (depends on 16)

The method of claim 16, wherein a ratio of the second duration to the first duration is about 0.2 to about 1.6.

### Claim 18 (depends on 16)

The method of claim 16, wherein a ratio of the third duration to the first duration is about to about 1.6.

### Claim 19 (depends on 16)

The method of claim 16, wherein a ratio of the fourth duration to the first duration is about 0.2 to about 1.0.

### Claim 20 (depends on 16)

The method of claim 16, wherein the gate dielectric layer is formed such that it is thicker above each one of the semiconductor layers than below the respective one of the semiconductor layers.