# US 11,908,744 B2 · Semiconductor device structure

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- Number: US 11,908,744 B2
- Document ID: US11908744B2
- Status: Granted
- Kind: B2
- Application number: 17/818,443
- Filed: 2022-08-09
- Published: 2022-12-01
- Granted: 2024-02-20
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Lin-Yu Huang; Sheng-Tsung Wang; Jia-Chuan You; Chia-Hao Chang; Tien-Lu Lin; Yu-Ming Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US11908744B2

## CPC

- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/667: {by liquid etching only}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a substrate;
a first fin structure protruding from the substrate;
an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure;
a gate stack formed over the first fin structure and the isolation layer;
a first source/drain structure formed over the first fin structure and spaced apart from the gate stack;
a contact structure formed over the first source/drain structure;
a dielectric structure formed through the contact structure; and
a cap layer formed over the contact structure,
wherein the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer, and the contact structure covers the top surface of the isolation layer, and wherein the cap layer and the dielectric structure has a second slope interface that slopes downwardly from a top surface of cap layer to the top surface of the contact structure.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the dielectric structure physically contacts the top surface of the isolation layer.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the cap layer vertically overlaps the first source/drain structure and the isolation layer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second fin structure protruding from the substrate; and
a second source/drain structure formed over the second fin structure,
wherein the contact structure continuously extends from the first source/drain structure to the second source/drain structure.

### Claim 5 (depends on 4)

The semiconductor device structure as claimed in claim 4, wherein the dielectric structure and the second source/drain structure are at opposite sides of the first source/drain structure.

### Claim 6

A semiconductor device structure, comprising:
a substrate;
a fin structure protruding from the substrate and having a first longitudinal axis along a first direction;
a gate stack formed across the fin structure along a second direction different from the first direction;
a source/drain structure attached to the fin structure;
a contact structure formed over the source/drain structure and having a second longitudinal axis along the second direction; and
a dielectric structure formed through the contact structure and having a top surface and a bottom surface, wherein the dielectric structure has a first dimension at the top surface along the second direction and a second dimension at the bottom surface along the second direction, and the first dimension is greater than the second dimension, and the bottom surface of the dielectric structure is no lower than a bottom surface of the contact structure.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a liner layer laterally sandwiched between the contact structure and the gate stack along the first direction, wherein the liner layer vertically covers the source/drain structure.

### Claim 8 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a first cap layer formed over the contact structure, wherein the first cap layer has a third dimension at its top portion along the second direction and a fourth dimension at its bottom portion along the second direction, and the fourth dimension is greater than the third dimension.

### Claim 9 (depends on 8)

The semiconductor device structure as claimed in claim 8, wherein the first cap layer has a fifth dimension at its top portion along the first direction and a sixth dimension at its bottom portion along the first direction, and the fifth dimension is greater than the sixth dimension.

### Claim 10 (depends on 8)

The semiconductor device structure as claimed in claim 8, further comprising:
a second cap layer formed over the gate stack, wherein the second cap layer has a seventh dimension at its top portion along the first direction and an eighth dimension at its bottom portion along the first direction, and the seventh dimension is greater than the eighth dimension.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the second cap layer is thicker than the first cap layer.

### Claim 12 (depends on 6)

The semiconductor device structure as claimed in claim 6, wherein the bottom surface of the dielectric structure is substantially level with the bottom surface of the contact structure.

### Claim 13

A semiconductor device structure, comprising:
a fin structure protruding from a substrate and extending along a first direction;
a gate stack formed over the substrate and extending along a second direction different from the first direction;
a dielectric structure spaced apart from the gate stack along the second direction, wherein the dielectric structure has a slope sidewall surface;
source/drain structures formed at opposite sides of the gate stack along the first direction;
a contact structure formed over the source/drain structures and extending along and in contact with a lower portion of the slope sidewall surface of the dielectric structure; and
a first cap layer vertically overlapping the contact structure and extending along and in contact with an upper portion of the slope sidewall surface of the dielectric structure.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, further comprising:
an isolation layer formed around the fin structure,
wherein an end of the slope sidewall surface of the dielectric structure and a bottom surface of the contact structure joins at a top surface of the isolation layer.

### Claim 15 (depends on 13)

The semiconductor device structure as claimed in claim 13, further comprising:
a second cap layer formed over the gate stack,
wherein the first cap layer has a first dimension along a third direction and the second cap layer has a second dimension along the third direction, the third direction is substantially vertical to the first direction and the second direction, and the first dimension is smaller than the second dimension.

### Claim 16 (depends on 15)

The semiconductor device structure as claimed in claim 15, further comprising:
a liner layer sandwiched between the first cap layer and the second cap layer along the first direction, wherein the liner layer is in direct contact with the source/drain structures.

### Claim 17 (depends on 16)

The semiconductor device structure as claimed in claim 16, wherein the liner layer is in direct contact with the dielectric structure.

### Claim 18 (depends on 16)

The semiconductor device structure as claimed in claim 16, further comprising:
a spacer sandwiched between the liner layer and second cap layer along the first direction, wherein a top surface of the second cap layer is higher than a top surface of the spacer.

### Claim 19 (depends on 14)

The semiconductor device structure as claimed in claim 14, wherein an interface between the first cap layer and the dielectric structure and an interface between the source/drain structures and the dielectric structure are both coincident with a first surface.

### Claim 20 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the top surface of the cap layer is narrower than the top surface of the contact structure.