# US 11,908,743 B2 · Planar devices with consistent base dielectric

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- Number: US 11,908,743 B2
- Document ID: US11908743B2
- Status: Granted
- Kind: B2
- Application number: 17/485,601
- Filed: 2021-09-27
- Published: 2023-03-30
- Granted: 2024-02-20
- Earliest claimed: 2021-09-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Huimei Zhou; Andrew M. Greene; Julien Frougier; Ruqiang Bao; Jingyun Zhang; Miaomiao Wang; Dechao Guo
- Web page: https://patentgrep.com/patent/US11908743B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
forming a fill over a stack of semiconductor layers, the stack of semiconductor layers including a first sacrificial layer and a set of alternating second sacrificial layers and channel layers;
forming a dielectric fin over the stack of semiconductor layers;
etching away the first sacrificial layer and the second sacrificial layers, leaving the channel layers supported by the dielectric fin over an exposed substrate surface;
conformally depositing a dielectric layer on the exposed substrate surface, the dielectric layer having a consistent thickness across the exposed substrate surface; and
depositing a conductive material over the dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein conformally depositing the dielectric layer on the exposed substrate surface includes depositing high-k dielectric material directly on the exposed substrate surface.

### Claim 3 (depends on 1)

The method of claim 1, wherein depositing the conductive material over the dielectric layer includes depositing conductive material directly on the dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the conductive material is a work function metal.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dielectric fin prevents formation of source/drain structures on the channel layers during an epitaxial growth process.

### Claim 6 (depends on 1)

The method of claim 1, further comprising conformally depositing a dielectric liner on the stack of semiconductor layers, before forming the fill.

### Claim 7 (depends on 6)

The method of claim 6, further comprising etching away the dielectric liner from sidewalls of the stack of semiconductor layers, after forming the dielectric fin, leaving a portion of the dielectric liner on a top surface of the stack of semiconductor layers, under the dielectric fin.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the dielectric fin includes forming a pair of dielectric fins that cover respective sidewalls of the stack of semiconductor layers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first sacrificial layer and the second sacrificial layer are formed from silicon germanium, with the first sacrificial layer having a higher germanium concentration than the second sacrificial layers.

### Claim 10 (depends on 9)

The method of claim 9, wherein etching away the first sacrificial layer and the second sacrificial layers is performed with a single etching process.

### Claim 11

A semiconductor device, comprising:
a dielectric layer directly on a top surface of a substrate, the dielectric layer having a consistent thickness across the top surface and including a high-k dielectric;
a conductive layer on the dielectric layer that includes a work function metal;
a first dielectric fin on the substrate; and
a plurality of semiconductor layers, vertically stacked above the dielectric layer, supported by the first dielectric fin.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the semiconductor device has no source or drain structure in direct contact with the plurality of semiconductor layers.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising a dielectric liner between the first dielectric fin and the plurality of semiconductor layers.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the dielectric liner includes a top portion between the first dielectric fin and a top surface of an uppermost semiconductor layer in the plurality of semiconductor layers.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising a second dielectric fin, wherein the first dielectric fin and the second dielectric fin support respective sides of the plurality of semiconductor layers.

### Claim 16

An integrated chip, comprising:
a transistor device, comprising:
a body isolation layer on a substrate;
a nanosheet channel over the body isolation layer;
a gate conductor; and
a gate dielectric material between the gate conductor and the body isolation layer; and
a planar device, comprising:
a gate dielectric material directly on a top surface of the substrate, the gate dielectric material having a consistent thickness across the top surface;
a conductive layer on the dielectric layer;
a first dielectric fin on the substrate; and
a semiconductor layer supported by the first dielectric fin.

### Claim 17 (depends on 16)

The integrated chip of claim 16, wherein the planer device has no source or drain structure in direct contact with the semiconductor layer.

### Claim 18 (depends on 16)

The integrated chip of claim 16, wherein the planar device further comprises a second dielectric fin, wherein the first dielectric fin and the second dielectric fin support respective sides of the semiconductor layer.

### Claim 19 (depends on 16)

The integrated chip of claim 16, wherein the gate dielectric material of the planar device includes the same high-k gate dielectric material as the gate dielectric material of the transistor device.