# US 11,908,742 B2 · Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,908,742 B2
- Document ID: US11908742B2
- Status: Granted
- Kind: B2
- Application number: 17/347,332
- Filed: 2021-06-14
- Published: 2021-10-07
- Granted: 2024-02-20
- Earliest claimed: 2016-12-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Jing Lee; Jeng-Wei Yu; Li-Wei Chou; Tsz-Mei Kwok; Ming-Hua Yu
- Web page: https://patentgrep.com/patent/US11908742B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/01: Manufacture or treatment
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a first fin and a second fin protruding from the semiconductor substrate;
a first epitaxial material located on the first fin;
a second epitaxial material located on the second fin, each of the first and second epitaxial materials bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins; and
a merged epitaxial material over and in contact with the first and second epitaxial materials.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface of the merged epitaxial material between the first and second fins has a first portion slanted with respect to a top surface of the semiconductor substrate and a second portion slanted with respect to the top surface of the semiconductor substrate, and wherein the first and second portions of the bottom surface of the merged epitaxial material intersect at an apex of the bottom surface.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the bottom surface has a height-to-span ratio less than about 0.5.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the bottom surface has a height-to-span ratio less than about 0.25.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein the apex of the bottom surface of the merged epitaxial material is above topmost portions of the first and second epitaxial material.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the merged epitaxial material is partially embedded in each of the first and second epitaxial materials.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface of the merged epitaxial material is substantially parallel to a top surface of the semiconductor substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dielectric layer on sidewalls of the first and second epitaxial materials.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein each of the first and second epitaxial materials has a portion laterally stacked between the dielectric layer and the merged epitaxial material.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the merged epitaxial material has a different dopant concentration than the first and second epitaxial materials.

### Claim 11

A semiconductor device, comprising:
a substrate;
first and second fins over the substrate and extending upwardly in a first direction;
an epitaxial material comprising a first portion, a second portion, and a third portion, wherein the first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions, wherein each of the first and second portions has a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, wherein the third portion has a bottom surface bended upwardly with an apex located between the first and second fins, and wherein in the cross-sectional plane the bottom surface has a first straight line and a second straight line intersecting at the apex; and
a conductive feature in contact with the epitaxial material.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the third portion of the epitaxial material has a different dopant concentration than the first and second portions of the epitaxial material.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the conductive feature comprises a sidewall extending in the first direction, and the sidewall is in contact with the epitaxial material.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first straight line is located between the first fin and the apex, and the second straight line is located between the second fin and the apex.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the epitaxial material has an external sidewall surface slanted with respect to a top surface of the substrate, and the external sidewall surface is in contact with the conductive feature.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the bottom surface has a height-to-span ratio less than about 0.25.

### Claim 17

A semiconductor device, comprising:
a substrate;
a semiconductor fin protruding from the substrate and extending upwardly in a first direction;
a source/drain (S/D) feature including a first portion over the semiconductor fin and a second portion over the first portion, wherein a top surface of the first portion of the S/D feature bends downward towards the substrate in a cross-sectional plane perpendicular to a lengthwise direction of the semiconductor fin, wherein the S/D feature comprises a first slanted sidewall and a second slanted sidewall, and wherein the first and second slanted sidewalls intersect; and
a conductive feature disposed on the S/D feature, wherein a portion of the conductive feature is landed on the first slanted sidewall and a bottom of the conductive feature is closer to the substrate than an intersected portion of the first and second slanted sidewalls, the conductive feature comprises a sidewall extending in the first direction, and a bottom of the sidewall is lower than a topmost portion of the S/D feature and spaced apart from the bottom of the conductive feature.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a bottommost portion of the conductive feature is spaced apart form a bottommost portion of the sidewall.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a width of the conductive feature below the intersected portion of the first and second slanted sidewalls is less than a width of the conductive feature above the S/D feature.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the bottom of the conductive feature is laterally offset from the bottom of the sidewall.