# US 11,908,739 B2 · Flat metal features for microelectronics applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,739 B2 - Document ID: US11908739B2 - Status: Granted - Kind: B2 - Application number: 17/098,128 - Filed: 2020-11-13 - Published: 2021-03-18 - Granted: 2024-02-20 - Earliest claimed: 2017-06-05 - Assignees: Adeia Semiconductor Technologies LLC - Applicants: Adeia Semiconductor Technologies LLC - Inventors: Cyprian Emeka Uzoh - Web page: https://patentgrep.com/patent/US11908739B2 ## CPC - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10P 52/403: {of conductive or resistive materials} - H10W 20/033: {in openings in dielectrics} - H10W 20/044: {for electroless plating} - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/058: {by depositing on sacrificial masks, e.g. using lift-off} - H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation} - H10W 20/092: {by smoothing the dielectric parts} - H10W 20/4405: {the principal metal being aluminium} - H10W 20/4421: {the principal metal being copper} - H10W 20/4432: {the principal metal being a noble metal, e.g. gold} - H10W 20/4441: {the principal metal being a refractory metal} - H10W 72/019: {of bond pads} - H10W 72/01931: {using blanket deposition} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01955: {by using masks} - H10W 72/90: Bond pads, in general - H10W 72/941: {Dispositions of bond pads} - H10W 80/011: {Manufacture or treatment of pads or other interconnections to be direct bonded} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features. ## Claims ### Claim 1 An apparatus comprising: a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, the first conductive layer-filled cavity having a first width of at least 5 microns and a first depth that is less than the first width; and a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein the second conductive layer-filled cavity has a second width and a second depth that is less than the second width and wherein a width of a grain size of a conductor within the second conductive layer-filled cavity is more than 5% of the width of one of (i) the first conductive layer-filled cavity or (ii) the second conductive layer-filled cavity wherein the first bonding surface is bonded to the second bonding surface. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: a first barrier layer over a surface of the first conductive layer-filled cavity; and a second barrier layer over a surface of the second conductive layer-filled cavity. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first depth is between about 1 to 7 microns and the second depth is between about 1 to about 7 microns. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the first bonding surface is bonded to the second bonding surface via a hybrid bond direct bond. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the first width of the first is 2 to 5 times the second width. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the first bonding surface comprise a first flat conductive metal feature having a width of at least 5 microns on the first substrate, wherein a dishing concavity across the width of the first flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the first flat conductive metal feature; and the second bonding surface comprise a second flat conductive metal feature having a width of at least 5 microns on the second substrate, wherein a dishing concavity across the width of the second flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the second flat conductive metal feature. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the first flat conductive metal feature and the second flat conductive metal feature are from a group consisting of: a flat conductive metal feature with a width of at least 10 microns (μm) and a maximum dishing of less than 10 nanometers (nm); a flat conductive metal feature with a width of at least 10 μm and a maximum dishing of less than 10 nanometers per micron (nm/μm) of depth of the flat conductive metal feature; and a bonded metallic feature larger than 10 μm. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the width of the first flat conductive metal feature and the width the second flat conductive metal feature are more than 25 microns and the dishing concavity of the first flat conductive metal feature and the second flat conductive metal feature are each less than 10 nanometers. ### Claim 10 (depends on 7) The apparatus of claim 7, wherein the width of the first flat conductive metal feature and the width of the second flat conductive metal feature are each between 26-150 microns and the dishing concavity of the first flat conductive metal feature and the width of the second flat conductive metal feature are each less than 20 nanometers. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein at least one of the first substrate or the second substrate comprise a microelectronic device. ### Claim 12 An apparatus comprising: a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, wherein a conductive layer of the first conductive layer-filled cavity has a width of at least 10 microns, wherein a grain size of a conductor within the first conductive layer-filled cavity is more than 5% of the width of the first conductive layer-filled cavity; and a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein a width of a conductive layer of the second conductive layer-filled cavity is 2-10 times the width of the conductive layer of the first conductive layer filled cavity, wherein the first bonding surface is bonded to the second bonding surface. ### Claim 13 (depends on 12) The apparatus of claim 12, further comprising: a first barrier layer over a surface of the first conductive layer-filled cavity; and a second barrier layer over a surface of the second conductive layer-filled cavity. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein: the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein at least one of the first substrate or the second substrate comprise a microelectronic device.