# US 11,908,733 B2 · Substrate processing method and device manufactured by using the same

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- Number: US 11,908,733 B2
- Document ID: US11908733B2
- Status: Granted
- Kind: B2
- Application number: 17/741,401
- Filed: 2022-05-10
- Published: 2022-08-25
- Granted: 2024-02-20
- Earliest claimed: 2018-05-28
- Assignees: ASM IP Holding B.V.
- Applicants: ASM IP Holding B.V.
- Inventors: Yoon Ki Min
- Web page: https://patentgrep.com/patent/US11908733B2

## CPC

- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10P 50/283: {by chemical means}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate;
at least one memory cell string extending to protrude on the substrate;
a first word line connected to a first memory cell among the at least one memory cell string; and
a second word line connected to a second memory cell among the at least one memory cell string,
wherein at least one of the first word line and the second word line comprises:
a word line conductive layer extending toward a channel;
a first conductive layer on the word line conductive layer; and
a second conductive layer on the first conductive layer,
wherein the first conductive layer comprises a surface region and an inner region under the surface region,
the first conductive layer comprises an upper recess in the surface region and a lower recess in the inner region, and
an extension length of the upper recess is different from an extension length of the lower recess.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the extension length of the upper recess is greater than the extension length of the lower recess.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second conductive layer protrudes from the surface region of the first conductive layer in a first direction.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the second conductive layer protrudes from the surface region of the first conductive layer in a second direction opposite to the first direction.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second conductive layer protrudes from the inner region of the first conductive layer in a first direction.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the surface region of the first conductive layer protrudes from the second conductive layer in a second direction opposite to the first direction.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the second conductive layer comprises a recess.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the extension length of the recess of the second conductive layer is less than the extension length of the upper recess of the first conductive layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the extension length of the recess of the second conductive layer is less than the extension length of the lower recess of the first conductive layer.

### Claim 10 (depends on 5)

The semiconductor device of claim 5, further comprising a via contact connected to the second conductive layer.

### Claim 11

A semiconductor device comprising:
a substrate;
at least one memory cell string extending to protrude on the substrate;
a first word line connected to a first memory cell among the at least one memory cell string; and
a second word line connected to a second memory cell among the at least one memory cell string,
wherein at least one of the first word line and the second word line comprises:
a word line conductive layer extending toward a channel;
a first conductive layer on the word line conductive layer; and
a second conductive layer on the first conductive layer,
an extension length of a first recess of the first conductive layer is different from an extension length of a second recess of the second conductive layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the extension length of the first recess of the first conductive layer is greater than the extension length of the second recess of the second conductive layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first recess of the first conductive layer comprises an upper recess and a lower recess under the upper recess.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the extension length of the upper recess is different from the extension length of the lower recess.

### Claim 15

A semiconductor device comprising:
a substrate;
at least one memory cell string extending to protrude on the substrate;
a first word line connected to a first memory cell among the at least one memory cell string; and
a second word line connected to a second memory cell among the at least one memory cell string,
wherein at least one of the first word line and the second word line comprises:
a word line conductive layer extending toward a channel; and
a first conductive layer on the word line conductive layer,
wherein the first conductive layer comprises a surface region and an inner region under the surface region,
the first conductive layer comprises an upper recess in the surface region and a lower recess in the inner region, and
an extension length of the upper recess is different from an extension length of the lower recess.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising a via contact on the first conductive layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a second conductive layer between the first conductive layer and the via contact.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein an additional upper recess is formed between the inner region and the second conductive layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the additional upper recess is located opposite to the upper recess.